AZ100LVEL16VT
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)
-40°C
0°C
25°C
85°C
Symbol
Characteristic
Unit
Min
3955
3915
3075
Max
4165
4120
3445
Min
4005
3975
3100
Max
4165
4120
3338
Min
4005
3975
3100
Max
4165
4120
3338
Min
4005
3975
3100
Max
4165
4120
3338
VOH
VOH
VOL
Output HIGH Voltage1,3
Output HIGH Voltage1,5
Output LOW Voltage1,3,5
Input HIGH Voltage
D/D¯, EN/E¯N¯ (PECL)1
EN (CMOS/TTL)
mV
mV
mV
VIH
VIL
3835
2000
4120
VCC
3835
2000
4120
VCC
3835
2000
4120
VCC
3835
2000
4120
VCC
mV
mV
Input LOW Voltage
D/D¯, EN/E¯N¯ (PECL)1
EN (CMOS/TTL)
3190
GND
3610
0.5
3525
800
3750
3190
GND
3610
0.5
3525
800
3750
3190
GND
3610
0.5
3525
800
3750
3190
GND
3610
0.5
3525
800
3750
VBB
IIL
IIH
Reference Voltage1
mV
μA
μA
mA
Input LOW Current EN4
Input HIGH Current EN4
Power Supply Current2
150
48
150
48
150
48
150
54
IEE
1.
2.
3.
4.
5.
For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
Specified with VEEP and CS-SEL open for VTL and VTX. Subtract 4mA for VTNA, VTNB, VTNC & VTND.
Specified with VEEP and CS-SEL connected to VEE for VTL and VTX only.
Specified with EN-SEL open for VTL and VTX only.
Specified with QHG/Q¯HG connected with 50 Ω to VCC –2V for VTNA, VTNB, VTNC & VTND.
AC Characteristics (VEE = -3.0V to -5.5V; VCC = GND or VEE = GND; VCC = +3.0V to +5.5V)
-40°C
Typ
0°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Propagation Delay
tPLH / tPHL
D to Q/Q¯ Outputs1
D to QHG/Q¯HG Outputs1 (SE)
(SE)
400
550
20
400
550
20
400
550
20
430
630
20
ps
tSKEW
VPP
Duty Cycle Skew2
(SE)
5
5
5
5
ps
Minimum Input Swing3 DIFF
SE
80
160
80
160
80
160
80
160
mV
Output Rise/Fall Times1
(20% - 80%)
tr / tf
100
260
100
260
100
260
100
260
ps
1.
For VTL and VTX, output specified with VEEP and CS-SEL connected to VEE with an AC coupled 50Ω load. For VTNA, VTNB, VTNC &
VTND, AC coupled 50Ω on Q¯ to VCC –2V and DC coupled 50Ω to VCC –2V on QHG/Q¯HG.
2.
3.
Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
VPP is the minimum peak-to-peak input swing for which AC parameters guaranteed. The device has a voltage gain of ≈ 20 to Q/Q¯ outputs and a
voltage gain of ≈ 100 to QHG/Q¯HG outputs.
D
(PECL)
EN (VTL, VTX); EN (VTNA, VTNB)
EN (VTL, VTX, VTNC, VTND)
(CMOS)
Q
Q
QHG
QHG
TIMING DIAGRAM
April 2007 * REV - 9
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AZM [ ARIZONA MICROTEK, INC ]
