ARIZONA MICROTEK, INC.
AZ100LVEL16VT
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable
PACKAGE AVAILABILITY
FEATURES
•
•
High Bandwidth for ≥1GHz
Similar Operation as
PACKAGE
PART NUMBER
MARKING
P9
<Date Code>
NOTES
AZ100LVEL16VR except in
Disabled Condition: QHG is High
Operating Range of 3.0V to 5.5V
Minimizes External Components
Selectable Enable Polarity and
Threshold (CMOS/TTL or PECL)
Available in a 3x3 mm or 2x2 mm
MLP Package
MLP 8 (2x2x0.75)
AZ100LVEL16VTNA
1,2,3
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
P9+
<Date Code>
•
•
•
AZ100LVEL16VTNA+
AZ100LVEL16VTNB
AZ100LVEL16VTNB+
AZ100LVEL16VTNC
AZ100LVEL16VTNC+
AZ100LVEL16VTND
AZ100LVEL16VTND+
1,2
P8
MLP 8 (2x2x0.75)
1,2,4
1,2
<Date Code>
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
•
•
P8+
<Date Code>
S-Parameter (.s2p) and IBIS Model
Files Available on Arizona Microtek
Website
P2
MLP 8 (2x2x0.75)
1,2,5
1,2
<Date Code>
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
P2+
<Date Code>
P3
MLP 8 (2x2x0.75)
1,2
<Date Code>
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
P3+
<Date Code>
1,2
AZM
MLP 16 (3x3)
AZ100LVEL16VTL
16T
1,2
<Date Code>
AZM+
16T
<Date Code>
N/A
MLP 16 (3x3) RoHS
Compliant / Lead (Pb) AZ100LVEL16VTL+
Free
1,2
6
DIE
AZ100LVEL16VTXP
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
& Reel.
2
3
4
5
6
Date code format: “Y” or “YY” for year followed by “WW” for week.
Parts marked TNA for date codes prior to 4WW (prior to 2004).
Parts marked TNB for date codes prior to 4WW (prior to 2004).
Parts marked TNC for date codes prior to 4WW (prior to 2004).
Waffle Pack
DESCRIPTION
The AZ100LVEL16VT is a specialized oscillator gain stage with high gain output buffer including an enable.
The QHG/Q¯HG outputs have a voltage gain several times greater than the Q/Q¯ outputs.
MLP 16, 3x3 mm Package (VTL) or DIE (VTX)
The AZ100LVEL16VTL and AZ100LVEL16VTX provide a selectable enable input (EN) that allows
continuous oscillator operation. See truth table for the Enable function. If Enable pull-up is desired in the
CMOS/TTL mode, an external ≤20 kΩ resistor connecting EN to VCC will override the on-chip pull-down resistor.
When disabled, the QHG output is forced high and the Q¯HG output is forced low. The AZ100LVEL16VTL/VTX also
provides a VBB and 470 Ω internal bias resistors from D to VBB and D¯ to VBB. The VBB pin can support 1.5 mA
sink/source current. Bypassing VBB to ground with a 0.01 μF capacitor is recommended.
The outputs Q and Q¯ each have a selectable on-chip pull-down current source. See truth table below for current
source functions. External resistors may also be used to increase pull-down current to a maximum total of 25 mA.
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
AZM [ ARIZONA MICROTEK, INC ]
