AZ100LVEL16VT
Outputs QHG and Q¯HG each have an optional on-chip pull-down current source of 10 mA. When pad/pin VEEP is
left open (NC), the output current sources are disabled and the QHG /Q¯HG operate as standard PECL/ECL. When VEEP
is connected to VEE, the current sources are activated. The QHG /Q¯HG pull-down current can be decreased, by using a
resistor to connect VEEP to VEE. (See graph on page 5.)
MLP 8, 2x2 mm Package, VTNA, VTNB, VTNC & VTND Versions
All MLP 8, 2x2mm versions of the AZ100LVEL16VT provide an enable input that allows continuous oscillator
operation. VTNA and VTNB utilize an enable (E¯N¯ ) that operates in the PECL/ECL mode. When the E¯N¯ input is
LOW, the Q¯ and QHG/Q¯HG outputs follow the data inputs. When E¯N¯ is HIGH, the QHG output is forced high and the
Q¯HG output is forced low. VTNC and VTND utilize an enable (EN) that operates in the CMOS/TTL mode. When the
EN input is HIGH, the Q¯ and QHG/Q¯HG outputs follow the data inputs. When EN is LOW, the QHG output is forced
high and the Q¯HG output is forced low.
For VTNA and VTND, both D and D¯ inputs are brought out and tied to the VBB pin through 470 Ω internal bias
resistors. In VTNB and VTNC, the D¯ input is internally tied directly to the VBB pin and the D input is tied to the VBB
pin through a 470 Ω internal bias resistor. Bypassing VBB to ground with a 0.01 μF capacitor is recommended.
All MLP 8, 2x2mm versions (VTNA, VTNB, VTNC & VTND) have the Q, QHG, and Q¯HG current sources
disabled, while the Q¯ output operates with a 4 mA current source to VEE.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
ENABLE TRUTH TABLE
MLP 16 (VTL) or DIE (VTX)
4mA EA.
Q
EN-SEL
NC
NC
VEE*
VEE*
VEE*
VEE*
EN
Q/Q¯ QHG Q¯HG
Data Data Data
Data High Low
Data High Low
Data Data Data
Data High Low
Data Data Data
Q
D
D
CS-SEL
QHG
PECL Low, VEE or NC
PECL High or VCC
CMOS Low or VEE
CMOS High or VCC
NC, no external pull-up
NC, with ≤20kΩ to VCC
QHG
Ω
470
Ω
470
VBB
10mA EA.
*Connections to VCC or VEE must be less than 1Ω.
EN
VEEP
VEE
CMOS / TTL
THRESHOLD
EN-SEL
PIN DESCRIPTION
MLP 16 (VTL) or DIE (VTX)
PIN
FUNCTION
D/D¯
Q/Q¯
Data Inputs
Data Outputs
QHG/Q¯HG
VBB
EN-SEL
EN/E¯N¯
CS-SEL
VEEP
Data Outputs w/High Gain
Reference Voltage Output
Selects Enable Logic
CURRENT SOURCE TRUTH TABLE
MLP 16 (VTL) or DIE (VTX)
CS-SEL
NC
VEE*
VCC*
Q
4mA typ.
8mA typ.
0
Q¯
Enable Input
4mA typ.
8mA typ.
4mA typ.
Selects Q and Q¯ Current Source Magnitude
Optional QHG and Q¯HG Current Sources
Negative Supply
VEE
VCC
*Connections to VCC or VEE must be less than 1Ω.
Positive Supply
April 2007 * REV - 9
www.azmicrotek.com
2
AZM [ ARIZONA MICROTEK, INC ]
