AZ100LVEL16VT
LOGIC DIAGRAMS AND PINOUTS FOR 2x2mm PACKAGE
4mA
MLP 8, 2x2mm
Q
D
D
VEE
AZ100LVEL16VTNA
D
1
8
7
Q
QHG
QHG
VCC
2
3
4
D
VBB
EN
Ω
470
Ω
470
VBB
VEE
QHG
QHG
6
5
EN
MLP 8, 2x2mm
AZ100LVEL16VTNA
TOP VIEW
4mA
MLP 8, 2x2mm
Q
VEE
¯E¯N¯ operation follows PECL functionality.
Bottom Center Pad is the VEE return.
D
AZ100LVEL16VTNB
1
2
3
Q
8
SDee TimiΩng Diagram above.
QHG
470
QHG
VBB
VCC
QHG
QHG
7
VBB
EN
EN
6
5
VEE
4
MLP 8, 2x2mm
AZ100LVEL16VTNB
TOP VIEW
¯E¯N¯ operation follows PECL functionality.
See Timing Diagram above.
Bottom Center Pad may be left open
or tied to VEE. Pin 4 is the VEE return.
April 2007 * REV - 9
www.azmicrotek.com
8