AL462 Ultra HD FIFO Datasheet
11 DESIGN NOTES
11.1 General PCB Design Guideline
The AL462 is available in 249-Ball LFBGA.
Grounding
Analog and digital circuits are separated within the AL462 chip. To minimize system noise and prevent digital
system noise from entering the analog portion, a common ground plane for all devices, including the AL462, is
recommended. All the connections to the ground plan should have a very short lead. The ground plane should
be solid, not cross-hatched.
Power Planes
The analog portion of the AL462 and any associated analog circuitry should have their own power plane,
referred to as the analog power plane (AVDD18_PLL1/PLL2/PLL3). The analog power plane should be
connected to the digital power plane (VDD18, DVC18 and DVQ18) at a single point through a low resistance
ferrite bead.
The digital power plane should provide power to all digital logic on the PCB board, and the analog power plane
should provide power to all of the AL462 analog power pins and relevant analog circuitry.
The digital power plane should not be placed under the AL462 chip, the voltage reference or other analog
circuitry. Capacitive coupling of digital power supply noise from this layer to the AL462 and its related analog
circuitry can degrade signal integrity.
Power Supply Decoupling
Power supply connection pins should be individually decoupled. The decoupling capacitors should be placed as
close as possible to the AL462. The ground connection of the capacitor should go straight to the ground plane
through a via placed immediately adjacent to the pad. Ideally, the ground connection should be through 2 vias,
one placed on either side of the pad. For the best results, use 0.1µF ceramic chip capacitors. Lead lengths
should be minimized. The power pins should be connected to the bypass capacitors before being connected to
the power planes. 22µF capacitors should also be used between the AL462 power planes and the ground
planes to control low-frequency power ripple.
Digital Signal and Clock Interconnect
Digital signals to the AL462 should be isolated as much as possible from other analog circuitry. These signals
should not overlap the analog power plane. If this is not possible, coupling can be minimized by routing the
digital signal at a 90 degree angle across the analog signals. The 32-bit digital input bus, DI, should have the
same trace length; it also applies to DO, the output digital bus. The high frequency clock reference or crystal
should be handled carefully. Jitter and noise on the clock will degrade the data integrity. Keep the clock paths to
the AL462 as short as possible to reduce the amount of noise picked up.
©2016~2019 by AverLogic Technologies, Corp.
37/38
AVERLOGIC [ AVERLOGIC TECHNOLOGIES INC ]
