AL422
/RE Read Enable Input: /RE controls the operation of the data output. When /RE is pulled low, output
data is provided at the rising edge of the RCK cycle and the internal read address is incremented
automatically. /RE signal is fetched at the rising edge of the RCK cycle.
/OE Output Enable Input: /OE controls the enabling/disabling of the data output. When /OE is pulled low,
output data is provided at the rising edge of the RCK cycle. When /OE is pulled high, data output is
disabled and the output pins remain at high impedance status. /OE signal is fetched at the rising edge of
RCK cycle.
/WRST Write Reset Input: This reset signal initializes the write address to 0, and is fetched at the rising
edge of the WCK input cycle.
/RRST Write Reset Input: This reset signal initializes the read address to 0, and is fetched at the rising
edge of the RCK input cycle.
TST Test Pin: For testing purpose only. It should be pulled low for normal applications.
DEC: Decoupling cap pin, should be connected to a 1mF or 2.2mF capacitor to ground for 5V application.
For 3.3V application, the DEC pin can be simply connected to the 3.3V power with regular 0.1mF bypass
capacitor.
8.1 Memory Operation
Initialization
Apply /WRST and /RRST 0.1ms after power on, then follow the following instructions for normal operation.
Reset Operation
The reset signal can be given at any time regardless of the /WE, /RE and /OE status, however, they still need
to meet the setup time and hold time requirements with reference to the clock input. When the reset signal is
provided during disabled cycles, the reset operation is not executed until cycles are enabled again. After
WRST and RRST signals are pulled low, the data output and input start from address 0.
Write Operation
Data input DI7~DI0 is written into the write register at the WCK input when /WE is pulled low. The write
data should meet the setup time and hold time requirements with reference to the WCK input cycle.
Write operation is prohibited when /WE is pulled high, and the write address pointer is stopped at the
current position. The write address starts from there when the /WE is pulled low again. The /WE signal
needs to meet the setup time and hold time requirements with reference to the WCK input cycle.
© 1999~2006 by AverLogic Technologies, Corp.
Version 1.5
15
AVERLOGIC [ AVERLOGIC TECHNOLOGIES INC ]
