AL422
8.0 Functional Description
The AL422 is a video frame buffer consisting of DRAM that works like a FIFO which is long enough to
hold up to 819x480 bytes of picture information and fast enough to operate at 50MHz. The functional block
diagram is as follows:
Write
Data
Register
384k x8
Memory Cell
Array
Read
Data
Register
Input
Buffer
Output
Buffer
DI7~
DI0
DO7~
DO0
/OE
WCK
RCK
Write
Address
Counter
Read
Address
Counter
Timing Generator
& Arbiter
/WRST
/WE
/RRST
/RE
Refresh Address
Counter
AL422-03 Block Diagram
The I/O pinouts and functions are described as follows:
DI7~DI0 Data Input: Data is input on the rising edge of the cycle of WCK when /WE is pulled low
(enabled).
DO7~DO0 Data Output: Data output is synchronized with the RCK clock. Data is obtained at the rising
edge of the RCK clock when /RE is pulled low. The access time is defined from the rising edge of the RCK
cycle.
WCK Write Clock Input: The write data input is synchronized with this clock. Write data is input at the
rising edge of the WCK cycle when /WE is pulled low (enabled). The internal write address pointer is
incremented automatically with this clock input.
RCK Read Clock Input: The read data output is synchronized with this clock. Read data output at the
rising edge of the RCK cycle when /OE is pulled low (enabled). The internal read address pointer is
incremented with this clock input.
/WE Write Enable Input: /WE controls the enabling/disabling of the data input. When /WE is pulled low,
input data is acquired at the rising edge of the WCK cycle. When /WE is pulled high, the memory does not
accept data input. The write address pointer is stopped at the current position. /WE signal is fetched at the
rising edge of the WCK cycle.
© 1999~2006 by AverLogic Technologies, Corp.
Version 1.5
14
AVERLOGIC [ AVERLOGIC TECHNOLOGIES INC ]
