Switching Specifications (AC)
Over recommended temperature (T = -40° C to +105° C), supply voltage (2.7 V ≤ V ≤ 5.5 V). All typical specifications
A
DD
are at V = 5 V, T = 25° C
DD
A
Parameter
Symbol
Part Number
Min
Typ
Max
Units
Test Conditions
Propagation Delay Time to
Logic Low Output [1]
tPHL
ACPL-061L
46
80
ns
IF = 2 mA, VI = 5 V, RT = 1.68 kW,
CL= 15 pF, CMOS Signal Levels.
Propagation Delay Time to
Logic High Output [1]
tPLH
40
6
80
ns
IF = 2 mA, VI = 3.3 V, RT = 870 W,
CL= 15 pF, CMOS Signal Levels.
Figure 6a, 7a
Pulse Width
Pulse Width Distortion [2]
tPW
100
ns
ns
PWD
30
30
Propagation Delay Skew [3]
tPSK
tR
ns
ns
Output Rise Time
(10% – 90%)
12
10
12
10
47
38
IF = 2 mA, VI = 5 V, RT = 1.68 kW,
CL= 15 pF, CMOS Signal Levels.
ns
ns
ns
ns
ns
IF = 2 mA, VI = 3.3 V, RT = 870 W,
CL= 15 pF, CMOS Signal Levels.
Output Fall Time
(90% – 10%)
tF
IF = 2 mA, VI = 5 V, RT = 1.68 kW,
CL= 15 pF, CMOS Signal Levels.
IF = 2 mA, VI = 3.3 V, RT = 870 W,
CL= 15 pF, CMOS Signal Levels.
Propagation Delay Time to
Logic Low Output [1]
tPHL
tPLH
ACPL-C61L
90
90
IF = 5 mA, VI = 5 V, RT = 680 W,
CL= 15 pF, CMOS Signal Levels.
Propagation Delay Time to
Logic High Output [1]
IF = 5 mA, VI = 3.3 V, RT = 340 W,
CL= 15 pF, CMOS Signal Levels.
Figure 6b, 7b
Pulse Width
Pulse Width Distortion [2]
Propagation Delay Skew [3]
tPW
100
ns
ns
ns
ns
PWD
tPSK
9
40
30
Output Rise Time (10% – 90%) tR
12
10
12
10
66
47
IF = 5 mA, VI = 5 V, RT = 680 Ω,
CL= 15 pF, CMOS Signal Levels.
ns
ns
ns
ns
ns
IF = 5 mA, VI = 3.3 V, RT = 340 Ω,
CL= 15 pF, CMOS Signal Levels.
Output Fall Time (90% - 10%) tF
IF = 5 mA, VI = 5 V, RT = 680 Ω,
CL= 15 pF, CMOS Signal Levels.
IF = 5 mA, VI = 3.3 V, RT = 340 Ω,
CL= 15 pF, CMOS Signal Levels.
Propagation Delay Time
to Logic Low Output [1]
tPHL
ACNW261L
95
95
IF = 5 mA, VI = 5 V, RT = 680 W,
CL= 15 pF, CMOS Signal Levels.
IF = 5 mA, VI = 3.3 V, RT = 340 W,
CL= 15 pF, CMOS Signal Levels.
Figure 6c, 7c
Propagation Delay Time
to Logic High Output [1]
tPLH
Pulse Width
Pulse Width Distortion [2]
Propagation Delay Skew [3]
tPW
PWD
tPSK
tR
100
ns
ns
ns
ns
19
40
30
Output Rise Time
(10% – 90%)
12
10
12
10
9
IF = 5 mA, VI = 5 V, RT = 680 W,
CL= 15 pF, CMOS Signal Levels.
ns
ns
ns
ns
ns
IF = 5 mA, VI = 3.3 V, RT = 340 W,
CL= 15 pF, CMOS Signal Levels.
Output Fall Time
(90% - 10%)
tF
IF = 5 mA, VI = 5 V, RT = 680 W,
CL= 15 pF, CMOS Signal Levels.
IF = 5 mA, VI = 3.3 V, RT = 340 W,
CL= 15 pF, CMOS Signal Levels.
Propagation Delay Time of
tELH
tEHL
VEL = 0 V, VEH = 3 V, CL= 15 pF
Figure 8
[5]
Enable from VEH to VEL
Propagation Delay Time of
12
[6]
Enable from VEL to VEH
9
AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
