Switching Specifications (AC) (Continued)
Parameter
Symbol
Part Number
Min
Typ
Max
Units
Test Conditions
Static Common Mode
Transient Immunity at
Logic High Output [7]
| CMH
|
ACPL-061L
20
35
kV/μs
VCM = 1000 V, TA = 25° C, IF = 0 mA,
VI = 0V, CL= 15 pF, CMOS Signal
Levels. Figure 9
Static Common Mode
Transient Immunity at
Logic Low Output [8]
| CML |
CMRD
20
35
35
kV/μs
kV/μs
VCM = 1000 V TA = 25° C, IF = 2 mA,
VI = 5 V/3.3 V, CL= 15 pF, CMOS
Signal Levels. Figure 9
,
Dynamic Common Mode
Transient Immunity [9]
VCM = 1000 V TA = 25° C, IF = 2 mA,
,
VI = 5 V/3.3 V, 10 MBd data rate,
the absolute increase of PWD <10
ns. Figure 9
Static Common Mode
Transient Immunity at
Logic High Output [7]
| CMH
| CML |
CMRD
|
ACPL-C61L
20
20
35
35
35
kV/μs
kV/μs
kV/μs
VCM = 1000 V TA = 25° C, IF = 0 mA,
VI = 0 V, CL= 15 pF, CMOS Signal
Levels. Figure 9
,
Static Common Mode
Transient Immunity at
Logic Low Output [8]
VCM = 1000 V TA = 25° C, IF = 5 mA,
,
VI = 5 V/3.3 V, CL= 15 pF, CMOS
Signal Levels.
Dynamic Common Mode
Transient Immunity [9]
VCM = 1000 V TA = 25° C, IF = 5 mA,
,
VI = 5 V/3.3 V, 10 MBd datarate, the
absolute increase of PWD <10 ns.
Figure 9
Static Common Mode
Transient Immunity at
Logic High Output [7]
| CMH
| CML |
CMRD
|
ACNW261L
20
20
35
35
35
kV/μs
kV/μs
kV/μs
VCM = 1000 V TA = 25° C, IF = 0 mA,
VI = 0 V, CL= 15 pF, CMOS Signal
Levels. Figure 9
,
Static Common Mode
Transient Immunity at
Logic Low Output [8]
VCM = 1000 V TA = 25° C, IF = 5 mA,
,
VI = 5 V/3.3 V, CL= 15pF, CMOS
Signal Levels. Figure 9
Dynamic Common Mode
Transient Immunity [9]
VCM = 1000 V TA = 25° C, IF = 5 mA,
,
VI = 5 V/3.3 V, 10 MBd datarate, the
absolute increase of PWD <10 ns.
Figure 9
Package Characteristics
All typical at T = 25° C.
A
Parameter
Symbol
Part Number
Min
Typ
Max
Units
Test Conditions
Input-Output Insulation
VISO
ACPL-061L
3750
Vrms
RH < 50% for 1 min. TA = 25° C
ACPL-C61L
ACNW261L
5000
Input-Output Resistance
Input-Output Capacitance
Notes:
RI-O
CI-O
1012
0.6
W
pF
VI-O = 500 V
f = 1 MHz, TA = 25° C
1.
t
propagation delay is measured from the 50% (V or I ) on the rising edge of the input pulse to the 50% V of the falling edge of the V
PHL in F DD O
signal. t
propagation delay is measured from the 50% (V or I ) on the falling edge of the input pulse to the 50% level of the rising edge of the
in F
PLH
V
signal.
O
2. PWD is defined as |t
- t |.
PHL PLH
3.
t
is equal to the magnitude of the worst case difference in t
and/or t that will be seen between units at any given temperature within the
PSK
PHL PLH
recommended operating conditions.
4. The JEDEC registration for the ACPL-061L/ACPL-C61L/ACNW261L specifies a maximum I of -2.0 mA. Avago guarantees a maximum I of -1.6
EL
EL
mA.
5. The t
enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the rising
ELH
edge of the output pulse.
6. The t
enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the falling
EHL
edge of the output pulse.
7. CM is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
H
8. CM is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
L
9. CM is the maximum tolerable rate of the common mode voltage during data transmission to assure that the absolute increase of the PWD is less
D
than 10 ns.
10. When V pin is not used, connects V to V will result in improved CMR performance.
E
E
DD
10
AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
