VRAM
SMJ44C251B
MT42C4256
Austin Semiconductor, Inc.
FIGURE 18: Enhanced-Page-Mode Write-Cycle Timing
NOTES:
1. Referenced to CAS or W, whichever occurs last
NOTE B: A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing specifications.
TRG\ must remain high throughout the entire page-mode operation to assure page-mode cycle time if the late-write feature is used. If the early-write-
cycle timing is used, the state of TRG\ is a don’t care after the minimum period th(TRG) from the falling edge of RAS\.
WRITE-CYCLE STATE TABLE
STATE
CYCLE
1
L
L
H
H
2
L
L
L
L
3
H
L
L
H
4
5
Write Operation
Don't Care Valid Data
Write Mask Valid Data
Don't Care Valid Data
Don't Care Write Mask
Write-mask load/use, Write DQs to I/Os
Use previous write mask, Write DQs to I/Os
Load write mask on later of W\ fall and CAS\ fall
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
28
AUSTIN [ AUSTIN SEMICONDUCTOR ]
