SDRAM
AS4SD8M16
Austin Semiconductor, Inc.
INITIALIZE AND LOAD MODE REGISTER2
TIMING PARAMETERS
-75
-75
SYMBOL*
MIN
MAX
UNITS
SYMBOL*
MIN
MAX
UNITS
t
0.8
ns
t
1.5
ns
AH
CKS
t
1.5
2.5
2.5
7.5
10
ns
ns
ns
ns
ns
ns
t
0.8
1.5
2
ns
ns
AS
CH
CMH
t
t
CMS
3
t
t
t
CL
CK
MRD
t
t
t
66
20
ns
ns
CK(3)
CK(2)
RFC
t
RP
t
0.8
CKH
*CAS latency indicated in parentheses.
NOTES:
1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock HIGH time, all commands applied are NOP, with CKE a “Don’t Care”.
3. JEDEC and PC100 specify three clocks
4. Outputs are guaranteed High-Z after command is issued.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD8M16
Rev. 0.5 04/05
31
AUSTIN [ AUSTIN SEMICONDUCTOR ]
