DRAM
AS4LC4M16
Austin Semiconductor, Inc.
CAPACITANCE2
PARAMETER
SYM
MAX
UNIT
Input Capacitance: Address Pins
Input Capacitance: RAS\, CAS\, WE\, OE\
Input/Output Capacitance: DQ
C
C
C
5
pF
I1
I2
I0
7
7
pF
pF
AC ELECTRICAL CHARACTERISTICS5,6,7,8,9,10,11,12
(VCC = +3.3V ±0.3V)
-5
-6
MAX MIN MAX UNITS NOTES
DESCRIPTION
SYMBOL MIN
Access time from column address
Column-address setup to CAS\ precharge
Column-address hold time (referenced to RAS\)
Column-address setup time
Row-address setup time
25
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
12
38
0
15
45
0
tACH
tAR
28
28
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHD
tCHR
tCLCH
tCLZ
tCOH
tCP
0
0
Column address to WE\ delay time
Access time from CAS\
42
49
18
13
15
29
Column-address hold time
CAS\ pulse width
8
8
10
10
15
10
5
28
10,000
10,000
30, 32
CAS\ LOW to "Don't Care" during Self Refresh
CAS\ hold time (CBR Refresh)
Last CAS\ going LOW to first CAS\ to return HIGH
CAS\ to output in Low-Z
15
8
4, 31
31
5
0
0
29
Data output hold after CAS\ LOW
CAS\ precharge time
3
3
8
10
13, 33
29
Access time from CAS\ precharge
CAS\ to RAS\ precharge time
CAS\ hold time
28
35
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
5
38
5
5
45
5
31
31
CAS\ setup time (CBR Refresh)
CAS\ to WE\ delay time
4, 28
18, 28
31
28
8
35
10
10
0
WRITE command to CAS\ lead time
Data-in hold time
8
19, 29
19, 29
24, 25
20
Data-in setup time
0
tDS
Output disable
0
12
12
0
15
15
tOD
Output enable time
tOE
OE\ hold time from WE\ during
READ-MODIFY-WRITE cycle
tOEH
8
10
ns
25
OE\ HIGH hold time from CAS\ HIGH
OE\ HIGH pulse width
5
5
4
0
10
5
ns
ns
ns
ns
tOEHC
tOEP
tOES
tOFF
OE\ LOW to CAS\ HIGH setup time.
Output buffer turn-off delay
5
12
0
15
17, 24, 29
OE\ setup prior to RAS\ during HIDDEN REFRESH cycle
tORD
0
0
ns
AS4LC4M16
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.0 7/02
9
AUSTIN [ AUSTIN SEMICONDUCTOR ]
