DRAM
AS4LC4M16
Austin Semiconductor, Inc.
NOTES:
1. All voltages referenced to VSS.
17. tOFF (MAX) defines the time at which the output achieves
the open circuit condition and is not referenced to VOH or VOL
.
2. This parameter is sampled. VCC = +3.3V; f = 1 MHz; TA = 25°C. 18. tWCS, tRWD, tAWD, and tCWD are not restrictive operating
3. ICC is dependent on output loading and cycle rates. parameters. tWCS applies to EARLY WRITE cycles. If
Specified values are obtained with minimum cycle time and the
outputs open.
t
WCS > tWCS (MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout the entire
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle
time at which proper operation over the full temperature range
is ensured.
6. An initial pause of 100µs is required after power-up, followed
by eight RAS\ refresh cycles (RAS\-ONLY or CBR with WE\
HIGH), before proper device operation is ensured. The eight
cycle. tRWD, tAWD, and tCWD define READ-MODIFY-WRITE
cycles. Meeting these limits allows for reading and disabling
output data and then applying input data. OE\ held HIGH and
WE\ taken LOW after CAS\ goes LOW results in a LATE WRITE
(OE\-controlled) cycle. tWCS, tRWD, tCWD, and tAWD are not
applicable in a LATE WRITE cycle.
19. These parameters are referenced to CAS\ leading edge in
EARLY WRITE cycles and WE\ leading edge in LATE WRITE
or READ-MODIFY-WRITE operations are not possible.
20. If OE\ is tied permanently LOW, LATE WRITE, or READ-
MODIFY-WRITE operations are not possible.
RAS\ cycle wake-ups should be repeated any time the tREF
refresh requirements is exceeded.
7. AC characteristics assume tT = 2.5ns.
8. VIH (MIN) and VIL (MAX) are reference levels for measuring
timing of input signals. Transition times are measured between 21. A HIDDEN REFRESH may also be performed after a WRITE
cycle. In this case, WE\ is LOW and OE\ is HIGH.
22. RAS\-ONLY REFRESH that all 4,096 rows of the device be
refreshed at least once every 64ms.
23. CBR REFRESH for the device requires that at least 4,096
cycles be completed every 64ms.
VIH and VIL (or between VIL and VIH).
9. In addition to meeting the transition rate specification, all
input signals must transit between VIH and VIL (or between VIL
and VIH) in a monotonic manner.
10. If CAS\ and RAS\ = VIH, data output is High-Z.
24. The DQs go High-Z during READ cycles once tOD or tOFF
occur. If CAS\ stays LOW while OE\ is brought HIGH, the DQs
will go High-Z. If OE\ is brought back LOW (CAS\ still LOW),
the DQs will provide the previous read data.
11. If CAS\ = VIL, data output may contain data from the last
valid READ cycle.
12. Measured with a load equivalent to two TTL gates and
100pF; and VOL = 0.8V and VOH = 2V.
25. LATE WRITE and READ-MODIFY-WRITE cycles must
13. If CAS\ is LOW at the falling edge of RAS\, output data will
be maintained from the previous cycle. To initiate a new cycle
and clear the data-out buffer, CAS\ must be pulsed HIGH
have both tOD and tOEH met (OE\ HIGH during write cycle) in
order to ensure that the output buffers will be open during the
WRITE cycle. If OE\ is taken back LOW while CAS\ remains
LOW, the DQs will remain open.
for tCP.
26. Column address changed once each cycle.
27. The first CAS\ edge to transition LOW.
14. The tRCD (MAX) limit is no longer specified. tRCD (MAX)
was specified as a reference point only. If tRCD was greater than
the specified tRCD (MAX) limit, then access time was controlled
exclusively by tCAC (tRAC [MIN] no longer applied). With our
without the tRCD limit, tAA and tCAC must always be met.
15. The tRAD (MAX) limit is no longer specified. tRAD (MAX)
was specified as a reference point only. If tRAD was greater than
the specified tRAD (MAX) limit, then access time was controlled
exclusively by tAA (tRAC and tCAC no longer applied). With or
28. Output parameter (DQx) is referenced to corresponding CAS\
input; DQ0 - DQ7 by CASL\ and DQ8 - DQ15 by CASH\.
29. Each CASx\ must meet minimum pulse width.
30. The last CASx\ edge to transition HIGH.
31. Last falling CASx\ edge to first rising CASx\ edge.
32. Last rising CASx\ edge to first falling CASx\ edge.
33. Last rising CASx\ edge to next cycles last rising CASx\
edge.
34. Last CASx\ to go LOW.
without the tRAD (MAX) limit, tAA, tRAC, and tCAC must always
be met.
Notes continued on next page.
16. Either tRCH or tRRH must be satisfied for a READ cycle.
*64ms for IT version, 32ms for XT version.
AS4LC4M16
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.0 7/02
11
AUSTIN [ AUSTIN SEMICONDUCTOR ]
