DRAM
Austin Semiconductor, Inc.
4 MEG x 16 DRAM
Extended Data Out (EDO) DRAM
FEATURES
• Single +3.3V ±0.3V power supply.
• Industry-standard x16 pinout, timing, functions, and
package.
• 12 row, 10 column addresses
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS\-BEFORE-RAS\ (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data retention
• Level 1 Moisture Sensitivity Rating, JEDEC J-STD-020
AS4LC4M16
PIN ASSIGNMENT
(Top View)
50-Pin TSOP (DG)
OPTIONS
• Package(s)
50-pin TSOP (400-mil)
• Timing
50ns access
60ns access
• Refresh Rates
Standard Refresh
Self Refresh
• Operating Temperature Ranges
Military (-55°C to +125°C)
Industrial (-40°C to +85°C)
MARKINGS
DG
-5
-6
Configuration
Refresh
Row Address
Column Addressing
4 Meg x 16
4K
A0-A11
A0-A9
None
S*
XT
IT
NOTE:
The \ symbol indicates signal is active LOW.
*Contact factory for availability. Self refresh option available on IT
version only.
KEY TIMING PARAMETERS
t
RAC
SPEED t
RC
-5
84ns 50ns
-6
104ns 60ns
t
PC
20ns
25ns
t
AA
25ns
30ns
t
CAC
13ns
15ns
t
CAS
8ns
10ns
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS4LC4M16
Rev. 1.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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