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AS4LC4M16_05 参数 Datasheet PDF下载

AS4LC4M16_05图片预览
型号: AS4LC4M16_05
PDF下载: 下载PDF文件 查看货源
内容描述: 4 MEG ×16 DRAM扩展数据输出( EDO ) DRAM [4 MEG x 16 DRAM Extended Data Out (EDO) DRAM]
分类和应用: 动态存储器
文件页数/大小: 25 页 / 3754 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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DRAM  
AS4LC4M16  
Austin Semiconductor, Inc.  
The row address is latched by the RAS\ signal, then the  
column address is latched by CAS\. This device provides  
EDO-PAGE-MODE operation, allowing for fast successive data  
operations (READ, WRITE or READ-MODIFY-WRITE) within  
a given row.  
GENERAL DESCRIPTION  
The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic  
random-access memory device containing 67,108,864 bits and  
designed to operate from 3V to 3.6V. The device is functionally  
organized as 4,194,304 locations containing 16 bits each. The  
4,194,304 memory locations are arranged in 4,096 rows by 1,024  
columns. During READ or WRITE cycles, each location is  
uniquely addresses via the address bits: 12 row-address bits  
(A0 - A11) and 10 column-address bits (A0 - A9). In addition,  
both byte and word accesses are supported via the two CAS\  
pins (CASL\ and CASH\).  
The 4 Meg x 16 DRAM must be refreshed periodically in  
order to retain stored data.  
DRAM ACCESS  
Each location in the DRAM is uniquely addressable, as  
mentioned in the General Description. Use of both CAS\  
The CAS\ functionality and timing related to address and signals resulted in a word access via the 16 I/O pins  
control functions (e.g., latching column addresses or selecting (DQ0 - DQ15). Using only one of the two signals results in a  
CBR REFRESH) is such that the internal CAS\ signal is BYTE access cycle. CASL\ transitioning LOW selects an  
determined by the first external CAS\ signal (CASL\ or CASH\) access cycle for the lower byte (DQ0 - DQ7), and CASH\  
to transition LOW and the last to transition back HIGH. The transitioning LOW selects an access cycle for the upper byte  
CAS\ functionality and timing related to driving or latching data (DQ8-DQ15). General byte and word access timing is shown in  
is such that each CAS\ signal independently controls the Figures 1 and 2.  
associated either DQ pins.  
FIGURE 1: WORD and BYTE WRITE Example  
AS4LC4M16  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
Rev. 1.1 6/05  
3
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