AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
EARLY WRITE CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
t
CSH
t
RSH
t
t
t
t
CRP
RCD
CAS
CLCH
CASL/CASH
V
V
IH
IL
t
AR
t
t
t
t
RAD
RAH
RAL
CAH
t
t
ASC
ASR
t
ACH
V
V
IH
IL
ADDR
ROW
COLUMN
ROW
t
CWL
t
t
t
t
RWL
WCR
WCH
WP
t
WCS
t
t
WRH
WRP
WE
V
V
IH
IL
NOTE 1
t
t
DHR
DH
t
DS
V
IOH
IOL
DQ
OE
VALID DATA
V
V
V
IH
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
MIN MAX
10
-8
MIN MAX
10
SYM
tACH
tAR
tASC
tASR
tCAH
tCAS
MIN
15
45
0
MAX
MIN MAX
MIN MAX
UNITS
ns
SYM
tRAH
tRAL
tRAS
tRC
MIN
10
MAX
UNITS
ns
15
20
50
60
ns
30
35
40
ns
0
0
ns
60 10,000
110
70 10,000
130
80 10,000
150
ns
0
0
0
ns
ns
10
12
15
ns
tRCD
tRP
14
40
13
15
10
45
0
45
14
50
15
15
12
55
0
50
20
60
0
60
ns
12 10,000
13 10,000
20 10,000
ns
ns
tCLCH 10
10
5
10
5
ns
tRSH
tRWL
tWCH
tWCR
tWCS
tWP
ns
tCRP
tCSH
tCWL
tDH
tDHR
tDS
5
ns
20
15
60
0
ns
50
15
10
45
0
55
15
12
55
0
60
20
15
55
0
ns
ns
ns
ns
ns
ns
ns
10
10
10
12
10
10
15
10
10
ns
ns
tWRH
tWRP
ns
tRAD
12
30
12
35
15
40
ns
ns
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-104
AUSTIN [ AUSTIN SEMICONDUCTOR ]
