AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
t
RWC
t
t
RP
RAS
V
V
IH
IL
RAS
CASL/CASH
ADDR
t
CSH
t
RSH
t
t
t
t t
CAS, CLCH
CRP
RCD
V
V
IH
IL
t
AR
t
t
RAL
RAD
t
t
t
t
ASC
RCS
CAH
ASR
RAH
t
ACH
V
V
IH
IL
ROW
COLUMN
ROW
t
t
t
t
RWD
CWL
RWL
WP
t
CWD
t
t
WRH
t
WRP
AWD
V
V
IH
IL
WE
NOTE 1
t
AA
t
RAC
t
CAC
t
t
DS
DH
t
CLZ
V
IOH
IOL
VALID D
VALID D
DQ
OE
OPEN
OPEN
V
OUT
IN
t
t
t
OE
OD
OEH
V
V
IH
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
tAA
tACH
MAX
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM MIN
tOE
tOEH
MAX
MIN
MAX
MIN
MAX
UNITS
ns
30
35
40
15
20
20
15
45
0
15
50
0
20
60
0
12
12
15
ns
tAR
tRAC
tRAD
tRAH
tRAL
tRAS
tRCD
tRCS
tRP
60
30
70
35
80
40
ns
tASC
tASR
tAWD
tCAC
tCAH
tCAS
12
10
30
12
10
35
15
10
40
ns
0
0
0
ns
55
60
65
ns
15
20
20
60 10,000
70 10,000 80 10,000
ns
10
12
15
14
0
45
14
0
50
20
0
60
ns
12 10,000
13 10,000 20 10,000
ns
tCLCH 10
10
0
10
0
40
13
50
15
180
90
15
12
10
10
60
15
200
105
20
15
10
10
ns
tCLZ
tCRP
tCSH
tCWD
tCWL
tDH
0
5
tRSH
ns
5
5
tRWC 150
ns
50
35
15
10
0
55
40
15
12
0
60
45
20
15
0
tRWD
tRWL
tWP
tWRH
tWRP
80
15
10
10
10
ns
ns
ns
ns
tDS
ns
tOD
0
15
0
15
0
20
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-105
AUSTIN [ AUSTIN SEMICONDUCTOR ]
