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AS4DDR264M64PBG1R-38/IT 参数 Datasheet PDF下载

AS4DDR264M64PBG1R-38/IT图片预览
型号: AS4DDR264M64PBG1R-38/IT
PDF下载: 下载PDF文件 查看货源
内容描述: 64Mx64 DDR2 SDRAM W /共享控制总线集成塑封微电路 [64Mx64 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 28 页 / 243 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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iPEM  
4.2 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR264M64PBG1  
DDRII ICC SPECIFICATIONS AND CONDITIONS  
667 MHZ  
-3  
533 MHZ  
400 MHZ  
-5  
Parameter  
Symbol  
-38  
Units  
Operating Current: One bank active-precharge  
tCL=tCK(ICC), tRC=tRC(ICC), tRAS=tRAS MIN(ICC); CKE is  
HIGH, CS\ is HIGH between valid commands; Address bus  
switching, Data bus switching  
ICC0  
525  
600  
30  
480  
440  
480  
30  
mA  
Operating Current: One bank active-READ-precharge  
current  
IOUT=0ma; BL=4, CL=CL(ICC), AL=0; tCK = tCK(ICC), tRC-  
tRC(ICC), tRAS=tRAS MIN(ICC), tRCD=tRCD(ICC); CKE is  
HIGH, CS\ is HIGH between valid commands; Address bus is  
switching; Data bus is switching  
ICC1  
ICC2P  
ICC2Q  
ICC2N  
ICC3P  
520  
mA  
mA  
mA  
mA  
mA  
Precharge POWER-DOWN current  
All banks idle; tCK-tCK(ICC); CKE is LOW; Other control and  
address bus inputs are stable; Data bus inputs are floating  
30  
Precharge quiet STANDBY current  
All banks idle; tCK=tCK(ICC); CKE is HIGH, CS\ is HIGH;  
Other control and address bus inputs are stable; Data bus  
inputs are floating  
250  
270  
210  
230  
160  
180  
Precharge STANDBY current  
All banks idle; tCK-=tCK(ICC); CKE is HIGH, CS\ is HIGH;  
Other control and address bus inputs are switching; Data bus  
inputs are switching  
Active POWER-DOWN current  
MRS[12]=0  
125  
40  
105  
40  
95  
40  
All banks open; tCK=tCK(ICC); CKE is LOW;  
Other control and address inputs are stable; Data  
MRS[12]=1  
bus inputs are floating  
Active STANDBY current  
All banks open; tCK=tCK(ICC), tRAS MAX(ICC),  
tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH between valid  
commands; Other control and address bus inputs are  
switching; Data bus inputs are switching  
ICC3N  
ICC4W  
240  
685  
200  
565  
165  
485  
mA  
mA  
Operating Burst WRITE current  
All banks open, continuous burst writes; BL=4, CL=CL(ICC),  
tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH betwwn valid  
commands; Address bus inputs are switching; Data bus  
Operating Burst READ current  
All banks open, continuous burst READS, Iout=0mA; BL=4,  
CL=CL(ICC), AL=0; tCL=tCK(ICC), tRAS=tRAS MAX(ICC),  
tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH betwwn valid  
commands; Address and Data bus inputs switching  
ICC4R  
685  
565  
485  
mA  
Burst REFRESH current  
tCK=tCK(ICC); refresh command at every iRFC(ICC) interval;  
CKE is HIGH, CS\ is HIGH Between valid commands;  
Address bus inputs are switching; Data bus inputs are  
switching  
ICC5  
ICC6  
1000  
880  
800  
mA  
mA  
Self REFRESH current  
CK and CK\ at 0V; CKE </=0.2V; Other contro, address and  
data inputs are floating  
30  
30  
30  
Operating bank Interleave READ current:  
All bank interleaving READS, IOUT = 0mA; BL=4,  
CL=CL(ICC), AL=tRCD(ICC)-1xtCK(ICC); tCK=tCK(ICC),  
tRC=tRC(ICC), tRRD=tRRD(ICC); CKE is HIGH, CS\ is HIGH  
between valid commands; Address bus inputs are stable  
during deselects; Data bus inputs are switching  
ICC7  
1370  
1280  
1220  
mA  
Austin Semiconductor, Inc.  
Austin, Texas  
512.339.1188  
www.austinsemiconductor.com  
AS4DDR264M64PBG1  
Rev. 0.5 06/08  
23  
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