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AS4DDR264M64PBG1R-38/IT 参数 Datasheet PDF下载

AS4DDR264M64PBG1R-38/IT图片预览
型号: AS4DDR264M64PBG1R-38/IT
PDF下载: 下载PDF文件 查看货源
内容描述: 64Mx64 DDR2 SDRAM W /共享控制总线集成塑封微电路 [64Mx64 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 28 页 / 243 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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iPEM  
4.2 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR264M64PBG1  
AC OPERATING SPECIFICATIONS  
-3  
-38  
-5  
333MHz/667Mbps 266MHz/533Mbps 200MHz/400Mbps  
Parameter  
Symbol  
tCKAVG  
tCKAVG  
tCKAVG  
tCHAVG  
tCLAVG  
MIN  
3
MAX  
8
MIN  
MAX  
MIN  
MAX  
Units  
ns  
Clock Cycle Time  
Clock High Time  
CL=5  
CL=4  
CL=3  
3.75  
5
8
3.75  
5
8
5
5
8
ns  
8
8
8
ns  
0.48  
0.52  
0.52  
0.48  
0.52  
0.52  
0.48  
0.52  
0.52  
tCK  
Clock Low Time  
0.48  
tCH,tCL  
-125  
0.48  
tCH,tCL  
-125  
0.48  
tCH,tCL  
-125  
tCK  
ps  
Half Clock Period  
Clock Jitter - Period  
Min of  
tHP  
tJITPER  
125  
125  
125  
125  
125  
150  
ps  
tJIT DUTY  
tJITCC  
Clock Jitter - Half Period  
-125  
-125  
-150  
ps  
ps  
ps  
ps  
ps  
ps  
Clock Jitter - Cycle to Cycle  
250  
250  
250  
tERR2PER  
tERR4PER  
tERR10PER  
tERR50PER  
Cumulative Jitter error, 2 Cycles  
Cumulative Jitter error, 4 Cycles  
Cumulative Jitter error, 6-10 Cycles  
Cumulative Jitter error, 11-50 Cycles  
-175  
-250  
-350  
-450  
175  
250  
350  
450  
-175  
-250  
-350  
-450  
175  
250  
350  
450  
-175  
-250  
-350  
-450  
175  
250  
350  
450  
DQ hold skew factor  
tQHS  
tAC  
-
340  
450  
-
400  
500  
-
450  
600  
ps  
ps  
ps  
ps  
DQ output access time from CK/CK\  
Data-out High-Z window from CK/CK\  
DQS Low-Z window from CL/CK\  
-450  
-500  
-600  
tHZ  
tAC(MAX)  
tAC(MAX)  
tAC(MAX)  
tLZ1  
tAC(MIN)  
tAC(MAX)  
tAC(MIN)  
tAC(MAX)  
tAC(MIN)  
tAC(MAX)  
tLZ2  
DQ Low-Z window from CK/CK\  
2*tAC(MIN) tAC(MAX) 2*tAC(MIN) tAC(MAX) 2*tAC(MIN) tAC(MAX)  
ps  
ps  
ps  
tDSJEDEC  
tDHJEDEC  
DQ and DM input setup time relative to DQS  
DQ and DM input hold time relative to DQS  
100  
175  
0.35  
100  
225  
0.35  
150  
275  
0.35  
DQ and DM input pulse width (for each input)  
Data Hold skew factor  
tDIPW  
tQHS  
tCK  
ps  
340  
400  
400  
400  
450  
450  
DQ-DQS Hold, DQS to first DQ to go non valid, per access  
Data valid output window (DVW)  
tQH  
tHP-tQHS  
tQH-tDQSQ  
0.35  
tHP-tQHS  
tQH-tDQSQ  
0.35  
tHP-tQHS  
tQH-tDQSQ  
0.35  
ps  
tDVW  
ps  
DQS input-high pulse width  
tDQSH  
tDQSL  
tDQSCK  
tDSS  
tCK  
tCK  
ps  
DQS input-low pulse width  
0.35  
0.35  
0.35  
DQS output access time from CK/CK\  
DQS falling edge to CK rising - setup time  
DQS falling edge from CK rising-hold time  
DQS-DQ skew, DQS to last DQ valid, per group, per access  
DQS READ preamble  
-400  
-400  
-450  
0.2  
0.2  
0.2  
tCK  
tCK  
ps  
tDSH  
0.2  
0.2  
0.2  
tDQSQ  
tRPRE  
tRPST  
tWPRES  
tWPRE  
tWPST  
tDQSS  
240  
1.1  
0.6  
300  
1.1  
0.6  
350  
1.1  
0.6  
0.9  
0.4  
0.9  
0.4  
0.9  
0.4  
tCK  
tCK  
ps  
DQS READ postamble  
WRITE preamble setup time  
0
0
0
DQS WRITE preamble  
0.35  
0.4  
0.35  
0.4  
0.35  
0.4  
tCK  
tCK  
tCK  
tCK  
DQS WRITE postamble  
0.6  
0.6  
0.6  
Positive DQS latching edge to associated Clock edge  
WRITE command to first DQS latching transition  
-0.25  
0.25  
-0.25  
0.25  
-0.25  
0.25  
WL-tDQSS WL+tDQSS WL-tDQSS WL+tDQSS WL-tDQSS WL+tDQSS  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR264M64PBG1  
Rev. 0.5 06/08  
24  
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