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AS4DDR264M64PBG1R-38/IT 参数 Datasheet PDF下载

AS4DDR264M64PBG1R-38/IT图片预览
型号: AS4DDR264M64PBG1R-38/IT
PDF下载: 下载PDF文件 查看货源
内容描述: 64Mx64 DDR2 SDRAM W /共享控制总线集成塑封微电路 [64Mx64 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 28 页 / 243 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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iPEM  
4.2 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR264M64PBG1  
PRECHARGE COMMAND  
FIGURE 13 – PRECHARGE COMMAND  
The PRECHARGE command, illustrated in Figure 13, is used  
to deactivate the open row in a particular bank or the open  
row in all banks. The bank(s) will be available for a  
subsequent row activation a specified time (tRP) after the  
PRECHARGE command is issued, except in the case of  
concurrent auto precharge, where a READ or WRITE  
command to a different bank is allowed as long as it does  
not interrupt the data transfer in the current bank and does  
not violate any other timing parameters. Once a bank has  
been precharged, it is in the idle state and must be activated  
prior to any READ or WRITE commands being issued to that  
bank. A PRECHARGE command is allowed if there is no  
open row in that bank (idle state) or if the previously open  
row is already in the process of precharging. However, the  
precharge period will be determined by the last PRECHARGE  
command issued to the bank.  
CK#  
CK  
CKE  
HIGH  
CS#  
RAS#  
CAS#  
WE#  
PRECHARGE OPERATION  
ADDRESS  
A10  
Input A10 determines whether one or all banks are to be  
precharged, and in the case where only one bank is to be  
precharged, inputs BA2–BA0 select the bank. Otherwise  
BA2–BA0 are treated as “Don’t Care.” When all banks are to  
be precharged, inputs BA2–BA0 are treated as “Don’t Care.”  
ALL BANKS  
ONE BANK  
BA  
-
BA2, BA0  
Once a bank has been precharged, it is in the idle state and  
must be activated prior to any READ or WRITE commands  
being issued to that bank. tRPA timing applies when the  
PRECHARGE (ALL) command is issued, regardless of the  
number of banks already open or closed. If a single-bank  
PRECHARGE command is issued, tRP timing applies.  
DON’T CARE  
Note: BA = bank address (if A10 is LOW; otherwise "Don't Care").  
issued). The differential clock should remain stable and meet  
tCKE specifications at least 1 x tCK after entering self refresh  
mode. All command and address input signals except CKE are  
“Don’t Care” during self refresh.  
SELF REFRESH COMMAND  
The SELF REFRESH command can be used to retain data  
in the DDR2 SDRAM, even if the rest of the system is powered  
down. When in the self refresh mode, the DDR2 SDRAM  
retains data without external clocking. All power supply  
inputs (including VREF) must be maintained at valid levels  
upon entry/exit and during SELF REFRESH operation.  
The procedure for exiting self refresh requires a sequence of  
commands. First, the differential clock must be stable and meet  
tCK specifications at least 1 x tCK prior to CKE going back  
HIGH. Once CKE is HIGH (tCLE(MIN) has been satisfied with  
four clock registrations), the DDR2 SDRAM must have NOP or  
DESELECT commands issued for tXSNR because time is  
required for the completion of any internal refresh in progress.  
A simple algorithm for meeting both refresh and DLL  
requirements is to apply NOP or DESELECT commands for  
200 clock cycles before applying any other command.  
The SELF REFRESH command is initiated like a REFRESH  
command except CKE is LOW. The DLL is automatically  
disabled upon entering self refresh and is automatically  
enabled upon exiting self refresh (200 clock cycles must  
then occur before  
a
READ command can be  
Note: Self refresh not available at military temperature.  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR264M64PBG1  
Rev. 0.5 06/08  
19  
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