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AS4DDR264M64PBG1R-38/ET 参数 Datasheet PDF下载

AS4DDR264M64PBG1R-38/ET图片预览
型号: AS4DDR264M64PBG1R-38/ET
PDF下载: 下载PDF文件 查看货源
内容描述: 64Mx64 DDR2 SDRAM W /共享控制总线集成塑封微电路 [64Mx64 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 28 页 / 243 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
 浏览型号AS4DDR264M64PBG1R-38/ET的Datasheet PDF文件第1页浏览型号AS4DDR264M64PBG1R-38/ET的Datasheet PDF文件第2页浏览型号AS4DDR264M64PBG1R-38/ET的Datasheet PDF文件第3页浏览型号AS4DDR264M64PBG1R-38/ET的Datasheet PDF文件第4页浏览型号AS4DDR264M64PBG1R-38/ET的Datasheet PDF文件第6页浏览型号AS4DDR264M64PBG1R-38/ET的Datasheet PDF文件第7页浏览型号AS4DDR264M64PBG1R-38/ET的Datasheet PDF文件第8页浏览型号AS4DDR264M64PBG1R-38/ET的Datasheet PDF文件第9页  
iPEM  
4.2 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR264M64PBG1  
FIGURE 4 - POWER-UP AND INITIALIZATION  
Notes appear on page 7  
VDD  
V
L
DD  
t
1
VTD  
TT1  
V
V
REF  
Tk0  
Tl0  
Tm0  
Tg0  
Th0  
Ti0  
Tj0  
Te0  
Tf0  
Tc0  
Td0  
Tb0  
T0  
Ta0  
t
CK  
CK#  
CK  
t
t
CL  
CL  
SSTL_18  
LVCMOS  
2
2
LOW LEVEL  
CKE  
ODT  
3
LOW LEVEL  
16  
7
5
6
8
9
10  
REF  
11  
12  
13  
LM  
4
Comman d  
REF  
Valid  
LM  
PRE  
LM  
LM  
LM  
PRE  
LM  
LM  
NOP  
15  
DM  
3
Address  
Code  
Code  
Code  
A10 = 1  
Code  
Code  
Code  
Code  
A10 = 1  
Valid  
15  
High-Z  
High-Z  
High-Z  
DQS  
15  
DQ  
RTT  
t
t
t
t
t
t
t
t
t
MRD  
t
t
T = 400ns  
16  
T = 200µs (MIN)  
Power-up:  
RPA  
MRD  
MRD  
MRD  
MRD  
RPA  
RFC  
RFC  
MRD  
MRD  
(MIN)  
See note 17  
VDD and stable  
EMR(2)  
EMR(3)  
EMR  
MR without  
EMR with  
EMR with  
OCD exit  
clock (CK, CK#)  
DLL RESET OCD default  
Normal  
operation  
200 cycles of CK are require d before a READ comman d can be issued.  
MR with  
DLL RESET  
Indicates a break in  
time scale  
Dont care  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR264M64PBG1  
Rev. 0.5 06/08  
5
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