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AS4DDR264M64PBG1R-38/ET 参数 Datasheet PDF下载

AS4DDR264M64PBG1R-38/ET图片预览
型号: AS4DDR264M64PBG1R-38/ET
PDF下载: 下载PDF文件 查看货源
内容描述: 64Mx64 DDR2 SDRAM W /共享控制总线集成塑封微电路 [64Mx64 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 28 页 / 243 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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iPEM  
4.2 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR264M64PBG1  
CAS LATENCY (CL)  
DDR2 SDRAM also supports a feature called posted CAS  
additive latency (AL). This feature allows the READ command  
to be issued prior to tRCD (MIN) by delaying the  
The CAS latency (CL) is defined by bits M4-M6, as shown  
in Figure 5. CL is the delay, in clock cycles, between the  
registration of a READ command and the availability of the  
first bit of output data. The CL can be set to 3, 4, 5, 6 or 7  
clocks, depending on the speed grade option being used.  
internal command to the DDR2 SDRAM by AL clocks.  
Examples of CL = 3 and CL = 4 are shown in Figure 6; both  
assume AL = 0. If a READ command is registered at clock  
edge n, and the CL is m clocks, the data will be available  
nominally coincident with clock edge n+m (this assumes  
AL = 0).  
DDR2 SDRAM does not support any half-clock latencies.  
Reserved states should not be used as unknown operation  
or incompatibility with future versions may result.  
FIGURE 6 - CAS LATENCY (CL)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CK#  
CK  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Command  
DQS, DQS#  
DO  
n
DO  
n + 1  
DO  
n + 2  
DO  
n + 3  
DQ  
CL = 3 (AL = 0)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CK#  
CK  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Command  
DQS, DQS#  
DO  
n
DO  
n + 1  
DO  
n + 2  
DO  
n + 3  
DQ  
CL = 4 (AL = 0)  
Transitioning data  
Don’t care  
Notes: 1. BL = 4.  
2. Posted CAS# additive latency (AL) = 0.  
3. Shown with nominal tAC, tDQSCK, andtDQSQ.  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR264M64PBG1  
Rev. 0.5 06/08  
9
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