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AS4DDR264M64PBG1R-38/ET 参数 Datasheet PDF下载

AS4DDR264M64PBG1R-38/ET图片预览
型号: AS4DDR264M64PBG1R-38/ET
PDF下载: 下载PDF文件 查看货源
内容描述: 64Mx64 DDR2 SDRAM W /共享控制总线集成塑封微电路 [64Mx64 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 28 页 / 243 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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iPEM  
4.2 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR264M64PBG1  
DESCRIPTION  
The 4.2Gb DDR2 SDRAM, a high-speed CMOS, dynamic  
random-access memory containing 4,294,967,296 bits.  
Each of the four chips in the MCP are internally configured  
as 8-bank DRAM. The block diagram of the device is  
shown in Figure 2. Ball assignments and are shown in  
Figure 3.  
An auto precharge function may be enabled to provide a  
self-timed row precharge that is initiated at the end of the  
burst access.  
As with standard DDR SDRAMs, the pipelined, multibank  
architecture of DDR2 SDRAMs allows for concurrent  
operation, thereby providing high, effective bandwidth by  
hiding row precharge and activation time.  
The 4.2Gb DDR2 SDRAM uses a double-data-rate  
architecture to achieve high-speed operation. The double  
data rate architecture is essentially a 4n-prefetch  
architecture, with an interface designed to transfer two  
data words per clock cycle at the I/O balls. A single read  
or write access for the x64 DDR2 SDRAM effectively  
consists of a single 4n-bit-wide, one-clock-cycle data  
transfer at the internal DRAM core and four corresponding  
n-bit-wide, one-half-clock-cycle data transfers at the I/O  
balls.  
A self refresh mode is provided, along with a power-saving  
power-down mode.  
All inputs are compatible with the JEDEC standard for  
SSTL_18. All full drive-strength outputs are SSTL_18-  
compatible.  
GENERAL NOTES  
The functionality and the timing specifications  
discussed in this data sheet are for the DLLenabled  
mode of operation.  
A bidirectional data strobe (DQS, DQS#) is transmitted  
externally, along with data, for use in data capture at the  
receiver. DQS is a strobe transmitted by the DDR2  
SDRAM during READs and by the memory controller  
during WRITEs. DQS is edge-aligned with data for READs  
and center-aligned with data for WRITEs. There are  
strobes, one for the lower byte (LDQS, LDQS#) and one  
for the upper byte (UDQS, UDQS#).  
Throughout the data sheet, the various figures and  
text refer to DQs as DQ. The DQ term is to be  
interpreted as any and all DQ collectively, unless  
specifically stated otherwise. Additionally, each chip  
is divided into 2 bytes, the lower byte and upper  
byte. For the lower byte (DQ0 CDQ7), DM refers to  
LDM and DQS refers to LDQS. For the upper byte  
(DQ8 CDQ15), DM refers to UDM and DQS refers to  
UDQS.  
Complete functionality is described throughout  
the document and any page or diagram may have  
been simplified to convey a topic and may not be  
inclusive of all requirements.  
The MCP DDR2 SDRAM operates from a differential clock  
(CK and CK#); the crossing of CK going HIGH and CK#  
going LOW will be referred to as the positive edge of CK.  
Commands (address and control signals) are registered  
at every positive edge of CK. Input data is registered on  
both edges of DQS, and output data is referenced to both  
edges of DQS, as well as to both edges of CK.  
Any specific requirement takes precedence over a  
general statement.  
Read and write accesses to the DDR2 SDRAM are burst  
oriented; accesses start at a selected location and  
continue for a programmed number of locations in a  
programmed sequence. Accesses begin with the  
registration of anACTIVE command, which is then followed  
by a READ or WRITE command. The address bits  
registered coincident with theACTIVE command are used  
to select the bank and row to be accessed. The address  
bits registered coincident with the READ or WRITE  
command are used to select the bank and the starting  
column location for the burst access.  
INITIALIZATION  
DDR2 SDRAMs must be powered up and initialized  
in a predefined manner. Operational procedures other  
than those specified may result in undefined operation.  
The following sequence is required for power up and  
initialization and is shown in Figure 4 on page 5.  
The DDR2 SDRAM provides for programmable read or  
write burst lengths of four or eight locations. DDR2  
SDRAM supports interrupting a burst read of eight with  
another read, or a burst write of eight with another write.  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR264M64PBG1  
Rev. 0.5 06/08  
4
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