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AS4DDR264M64PBG1R-38/ET 参数 Datasheet PDF下载

AS4DDR264M64PBG1R-38/ET图片预览
型号: AS4DDR264M64PBG1R-38/ET
PDF下载: 下载PDF文件 查看货源
内容描述: 64Mx64 DDR2 SDRAM W /共享控制总线集成塑封微电路 [64Mx64 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 28 页 / 243 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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iPEM  
4.2 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR264M64PBG1  
RESET FUNCTION  
(CKE LOW Anytime)  
If CKE asynchronously drops LOW during any valid operation  
(including a READ or WRITE burst), the memory controller  
must satisfy the timing parameter tDELAY before turning off  
the clocks. Stable clocks must exist at the CK, CK# inputs of  
the DRAM before CKE is raised HIGH, at which time the  
normal initialization sequence must occur. The DDR2  
SDRAM device is now ready for normal operation after the  
initialization sequence.  
DDR2 SDRAM applications may go into a reset state  
anytime during normal operation. If an application enters  
a reset condition, CKE is used to ensure the DDR2 SDRAM  
device resumes normal operation after reinitializing. All  
data will be lost during a reset condition; however, the  
DDR2 SDRAM device will continue to operate properly if  
the following conditions outlined in this section are  
satisfied.  
The reset condition defined here assumes all supply  
voltages (VDD, VDDQ and VREF) are stable and meet all DC  
specifications prior to, during, and after the RESET  
operation. All other input pins of the DDR2 SDRAM device  
are a “Don’t Care” during RESET with the exception of  
CKE.  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR264M64PBG1  
Rev. 0.5 06/08  
20  
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