• Bit 6 – TXCn: USARTn Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted
out and there are no new data currently present in the transmit buffer (UDRn). The
TXCn flag bit is automatically cleared when a transmit complete interrupt is executed, or
it can be cleared by writing a one to its bit location. The TXCn flag can generate a Trans-
mit Complete interrupt (see description of the TXCIEn bit).
• Bit 5 – UDREn: USARTn Data Register Empty
The UDREn flag indicates if the transmit buffer (UDRn) is ready to receive new data. If
UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn flag
can generate a Data Register Empty interrupt (see description of the UDRIEn bit).
UDREn is set after a reset to indicate that the Transmitter is ready.
• Bit 4 – FEn: Frame Error
This bit is set if the next character in the receive buffer had a Frame Error when
received. I.e., when the first stop bit of the next character in the receive buffer is zero.
This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop
bit of received data is one. Always set this bit to zero when writing to UCSRnA.
• Bit 3 – DORn: Data OverRun
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the
receive buffer is full (two characters), it is a new character waiting in the Receive Shift
Register, and a new start bit is detected. This bit is valid until the receive buffer (UDRn)
is read. Always set this bit to zero when writing to UCSRnA.
• Bit 2 – UPEn: USARTn Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received
and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the
receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA.
• Bit 1 – U2Xn: Double the USARTn Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using
synchronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effec-
tively doubling the transfer rate for asynchronous communication.
• Bit 0 – MPCMn: Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCMn bit is writ-
ten to one, all the incoming frames received by the USARnT Receiver that do not
contain address information will be ignored. The Transmitter is unaffected by the
MPCMn setting. For more detailed information see “Multi-processor Communication
Mode” on page 187.
USART0 Control and Status
Register B – UCSR0B
Bit
7
RXCIE0
R/W
0
6
TXCIE0
R/W
0
5
UDRIE0
R/W
0
4
RXEN0
R/W
0
3
TXEN0
R/W
0
2
UCSZ02
R/W
0
1
0
TXB80
R/W
0
RXB80
UCSR0B
Read/Write
Initial Value
R
0
190
AT90CAN128
4250E–CAN–12/04
ATMEL [ ATMEL ]
