Output Compare Register A –
OCR2A
Bit
7
6
5
4
3
2
1
0
OCR2A[7:0]
R/W R/W
OCR2A
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
The Output Compare Register A contains an 8-bit value that is continuously compared
with the counter value (TCNT2). A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the OC2A pin.
Asynchronous operation
of the Timer/Counter2
Asynchronous Status
Register – ASSR
Bit
7
–
6
–
5
–
4
EXCLK
R/W
0
3
2
1
0
AS2
R/W
0
TCN2UB
OCR2UB
TCR2UB
ASSR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 7..5 – Reserved Bits
These bits are reserved for future use.
• Bit 4 – EXCLK: Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock
input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1)
pin instead of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous
operation is selected. Note that the crystal Oscillator will only run when this bit is zero.
• Bit 3 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O and the
crystal Oscillator connected to the Timer/Counter2 Oscillator (TOSC) does nor run.
When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator con-
nected to the Timer/Counter2 Oscillator (TOSC) or from external clock on TOSC1
depending on EXCLK setting. When the value of AS2 is changed, the contents of
TCNT2, OCR2A, and TCCR2A might be corrupted.
• Bit 2 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes
set. When TCNT2 has been updated from the temporary storage register, this bit is
cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be
updated with a new value.
• Bit 1 – OCR2UB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes
set. When OCR2A has been updated from the temporary storage register, this bit is
cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be
updated with a new value.
• Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit
becomes set. When TCCR2A has been updated from the temporary storage register,
154
AT90CAN128
4250E–CAN–12/04
ATMEL [ ATMEL ]
