3. Enter Power-save or ADC Noise Reduction mode.
•
When the asynchronous operation is selected, the 32.768 kHz Oscillator for
Timer/Counter2 is always running, except in Power-down and Standby modes. After
a Power-up Reset or wake-up from Power-down or Standby mode, the user should
be aware of the fact that this Oscillator might take as long as one second to
stabilize. The user is advised to wait for at least one second before using
Timer/Counter2 after power-up or wake-up from Power-down or Standby mode. The
contents of all Timer/Counter2 Registers must be considered lost after a wake-up
from Power-down or Standby mode due to unstable clock signal upon start-up, no
matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.
•
•
Description of wake up from Power-save mode when the timer is clocked
asynchronously: When the interrupt condition is met, the wake up process is started
on the following cycle of the timer clock, that is, the timer is always advanced by at
least one before the processor can read the counter value. After wake-up, the MCU
is halted for four cycles, it executes the interrupt routine, and resumes execution
from the instruction following SLEEP.
Reading of the TCNT2 Register shortly after wake-up from Power-save may give an
incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading
TCNT2 must be done through a register synchronized to the internal I/O clock
domain. Synchronization takes place for every rising TOSC1 edge. When waking up
from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will
read as the previous value (before entering sleep) until the next rising TOSC1 edge.
The phase of the TOSC clock after waking up from Power-save mode is essentially
unpredictable, as it depends on the wake-up time. The recommended procedure for
reading TCNT2 is thus as follows:
1. Write any value to either of the registers OCR2A or TCCR2A.
2. Wait for the corresponding Update Busy Flag to be cleared.
3. Read TCNT2.
•
During asynchronous operation, the synchronization of the interrupt flags for the
asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is
therefore advanced by at least one before the processor can read the timer value
causing the setting of the interrupt flag. The Output Compare pin is changed on the
timer clock and is not synchronized to the processor clock.
Timer/Counter2 Interrupt
Mask Register – TIMSK2
Bit
7
–
6
–
5
–
4
–
3
–
2
–
1
OCIE2A
R/W
0
0
TOIE2
R/W
0
TIMSK2
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 7..2 – Reserved Bits
These bits are reserved for future use.
• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one),
the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt
is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is
set in the Timer/Counter2 Interrupt Flag Register – TIFR2.
156
AT90CAN128
4250E–CAN–12/04
ATMEL [ ATMEL ]
