AT90CAN128
Figure 72 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.
Figure 72. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with
Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
(CTC)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
OCRnx
TOP
OCFnx
8-bit Timer/Counter
Register Description
Timer/Counter2 Control
Register A– TCCR2A
Bit
7
FOC2A
W
6
5
4
3
WGM21
R/W
0
2
1
CS21
R/W
0
0
WGM20 COM2A1 COM2A0
CS22
CS20
TCCR2A
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
• Bit 7 – FOC2A: Force Output Compare A
The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However,
for ensuring compatibility with future devices, this bit must be set to zero when TCCR2A
is written when operating in PWM mode. When writing a logical one to the FOC2A bit,
an immediate compare match is forced on the Waveform Generation unit. The OC2A
output is changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is
implemented as a strobe. Therefore it is the value present in the COM2A1:0 bits that
determines the effect of the forced compare.
A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode
using OCR2A as TOP.
The FOC2A bit is always read as zero.
151
4250E–CAN–12/04
ATMEL [ ATMEL ]
