AT90CAN128
implementations of the AVR architecture is so small that only SPL is needed. In this
case, the SPH Register will not be present.
Bit
15
SP15
SP7
7
Read/Write
R/W
R/W
Initial Value
0
0
14
SP14
SP6
6
R/W
R/W
0
0
13
SP13
SP5
5
R/W
R/W
0
0
12
SP12
SP4
4
R/W
R/W
0
0
11
SP11
SP3
3
R/W
R/W
0
0
10
SP10
SP2
2
R/W
R/W
0
0
9
SP9
SP1
1
R/W
R/W
0
0
8
SP8
SP0
0
R/W
R/W
0
0
SPH
SPL
Instruction Execution
Timing
This section describes the general access timing concepts for instruction execution. The
AVR CPU is driven by the CPU clock clk
CPU
, directly generated from the selected clock
source for the chip. No internal clock division is used.
Figure 7 shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast-access Register File concept. This is the basic pipelin-
functions per cost, functions per clocks, and functions per power-unit.
Figure 7.
The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clk
CPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 8 shows the internal timing concept for the Register File. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back
Figure 8.
Single Cycle ALU Operation
T1
T2
T3
T4
clk
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
Reset and Interrupt
Handling
The AVR provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate program vector in the program memory space. All
interrupts are assigned individual enable bits which must be written logic one together
13
4250E–CAN–12/04
ATMEL [ ATMEL CORPORATION ]
