AT90CAN128
Table 54. Waveform Generation Mode Bit Description(1)
WGM01 WGM00 Timer/Counter
Update of
TOV0 Flag
Mode
(CTC0)
(PWM0) Mode of Operation
TOP
OCR0A at Set on
0
1
2
3
0
0
1
1
0
1
0
1
Normal
0xFF
Immediate MAX
PWM, Phase Correct 0xFF
TOP
OCR0A Immediate MAX
0xFF TOP MAX
BOTTOM
CTC
Fast PWM
Note:
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-
initions. However, the functionality and location of these bits are compatible with
previous versions of the timer.
• Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the
COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit cor-
responding to the OC0A pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM01:0 bit setting. Table 55 shows the COM0A1:0 bit functionality when the
WGM01:0 bits are set to a normal or CTC mode (non-PWM).
Table 55. Compare Output Mode, non-PWM Mode
COM0A1
COM0A0
Description
0
0
1
1
0
1
0
1
Normal port operation, OC0A disconnected.
Toggle OC0A on compare match
Clear OC0A on compare match
Set OC0A on compare match
Table 56 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast
PWM mode.
Table 56. Compare Output Mode, Fast PWM Mode(1)
COM0A1
COM0A0
Description
0
0
1
0
1
0
Normal port operation, OC0A disconnected.
Reserved
Clear OC0A on compare match.
Set OC0A at TOP
1
1
Set OC0A on compare match.
Clear OC0A at TOP
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,
the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM
Mode” on page 100 for more details.
105
4250E–CAN–12/04
ATMEL [ ATMEL ]
