AT90CAN128
Figure 48. 16-bit Timer/Counter Block Diagram(1)
Count
TOVn
(Int.Req.)
Clear
Control Logic
Direction
clkTn
Clock Select
Edge
Detector
Tn
TOP BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
=
= 0
OCFnA
(Int.Req.)
Waveform
OCnA
=
Generation
OCRnA
OCFnB
(Int.Req.)
Fixed
TOP
Values
Waveform
OCnB
=
Generation
OCRnB
OCFnC
(Int.Req.)
Waveform
OCnC
=
Generation
OCRnC
( From Analog
Comparator Ouput )
ICFn (Int.Req.)
Edge
Detector
Noise
Canceler
ICPn
ICRn
TCCRnA
TCCRnB
TCCRnC
Note:
1. Refer to Figure 2 on page 4, Table 32 on page 71, and Table 41 on page 78 for
Timer/Counter1 and 3 pin placement and description.
Registers
The Timer/Counter (TCNTn), Output Compare Registers (OCRnx), and Input Capture
Register (ICRn) are all 16-bit registers. Special procedures must be followed when
accessing the 16-bit registers. These procedures are described in the section “Access-
ing 16-bit Registers” on page 111. The Timer/Counter Control Registers (TCCRnx) are
8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to
Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFRn).
All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSKn).
TIFRn and TIMSKn are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock
source on the Tn pin. The Clock Select logic block controls which clock source and edge
the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is
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4250E–CAN–12/04
ATMEL [ ATMEL ]
