AT90CAN128
Output Compare Register A –
OCR0A
Bit
7
6
5
4
3
2
1
0
OCR0A[7:0]
R/W R/W
OCR0
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
The Output Compare Register A contains an 8-bit value that is continuously compared
with the counter value (TCNT0). A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the OC0A pin.
Timer/Counter0 Interrupt
Mask Register – TIMSK0
Bit
7
–
6
–
5
–
4
–
3
–
2
–
1
OCIE0A
R/W
0
0
TOIE0
R/W
0
TIMSK0
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 7..2 – Reserved Bits
These are reserved bits for future use.
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one),
the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt
is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is
set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if
an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
Timer/Counter0 Interrupt Flag
Register – TIFR0
Bit
7
–
6
–
5
–
4
–
3
–
2
–
1
OCF0A
R/W
0
0
TOV0
R/W
0
TIFR0
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 1 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0
and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF0A is
cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A
(Timer/Counter0 Compare match Interrupt Enable), and OCF0A are set (one), the
Timer/Counter0 Compare match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0
(Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the
Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is
set when Timer/Counter0 changes counting direction at 0x00.
107
4250E–CAN–12/04
ATMEL [ ATMEL ]
