ATmega64A
8. System Clock and Clock Options
8.1
Clock Systems and their Distribution
Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocks
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in “Power Manage-
ment and Sleep Modes” on page 46. The clock systems are detailed below.
Figure 8-1. Clock Distribution
Asynchronous
Timer/Counter
General I/O
Modules
Flash and
EEPROM
ADC
CPU Core
RAM
clkADC
clkI/O
clkCPU
AVR Clock
Control Unit
clkASY
clkFLASH
Reset Logic
Watchdog Timer
Source Clock
Watchdog Clock
Clock
Multiplexer
Watchdog
Oscillator
Timer/Counter
Oscillator
External RC
Oscillator
Crystal
Oscillator
Low-frequency
Crystal Oscillator
Calibrated RC
Oscillator
External Clock
8.1.1
8.1.2
CPU Clock – clkCPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
I/O Clock – clkI/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted. Also note that address recognition in the TWI module is carried out asynchro-
nously when clkI/O is halted, enabling TWI address reception in all sleep modes.
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8160C–AVR–07/09
ATMEL [ ATMEL ]
