ATmega64A
2. Required only for fSCL > 100 kHz.
3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
5. This requirement applies to all ATmega64A Two-wire Serial Interface operation. Other devices connected to the Two-wire
Serial Bus need only obey the general fSCL requirement.
6. The actual low period generated by the ATmega64A Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than
6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.
7. The actual low period generated by the ATmega64A Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time require-
ment will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega64A devices connected to the bus may
communicate at full speed (400 kHz) with other ATmega64A devices, as well as any other device with a proper tLOW accep-
tance margin.
Figure 28-3. Two-wire Serial Bus Timing
t
HIGH
t
t
r
of
t
t
LOW
LOW
SCL
SDA
t
t
t
HD;DAT
SU;STA
HD;STA
t
SU;DAT
t
SU;STO
t
BUF
332
8160C–AVR–07/09
ATMEL [ ATMEL ]
