ATmega64A
28.6 Two-wire Serial Interface Characteristics
Table 28-4 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega64A Two-wire Serial
Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 28-3.
Table 28-4. Two-wire Serial Bus Requirements
Symbol Parameter
Condition
Min
-0.5
Max
0.3 VCC
VCC + 0.5
–
Units
V
VIL
Input Low-voltage
VIH
Vhys
Input High-voltage
0.7 VCC
V
(1)
(1)
(2)
Hysteresis of Schmitt Trigger Inputs
Output Low-voltage
0.05 VCC
V
VOL
tr(1)
3 mA sink current
10 pF < Cb < 400 pF(3)
0.1VCC < Vi < 0.9VCC
0
0.4
V
(3)(2)
(3)(2)
Rise Time for both SDA and SCL
Output Fall Time from VIHmin to VILmax
Spikes Suppressed by Input Filter
Input Current each I/O Pin
Capacitance for each I/O Pin
SCL Clock Frequency
20 + 0.1Cb
300
ns
ns
ns
µA
pF
kHz
(1)
tof
20 + 0.1Cb
250
tSP
Ii
Ci(1)
fSCL
0
-10
–
50(2)
(1)
10
10
fCK(4) > max(16fSCL, 250 kHz)(5)
0
400
VCC – 0,4V
----------------------------
3mA
fSCL ≤ 100 kHz
1000ns
Cb
-------------------
Ω
Ω
Rp
Value of Pull-up resistor
VCC – 0,4V
----------------------------
3mA
f
SCL > 100 kHz
300ns
---------------
Cb
fSCL ≤ 100 kHz
SCL > 100 kHz
4.0
0.6
4.7
1.3
4.0
0.6
4.7
0.6
0
–
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
tHD;STA
Hold Time (repeated) START Condition
Low Period of the SCL Clock
High period of the SCL clock
Set-up time for a repeated START condition
Data hold time
f
–
fSCL ≤ 100 kHz(6)
fSCL > 100 kHz(7)
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
–
tLOW
–
–
tHIGH
–
–
tSU;STA
tHD;DAT
tSU;DAT
f
SCL > 100 kHz
–
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
3.45
0.9
–
0
250
100
4.0
0.6
Data setup time
–
–
tSU;STO
Setup time for STOP condition
f
SCL > 100 kHz
–
Bus free time between a STOP and START
condition
tBUF
fSCL ≤ 100 kHz
4.7
–
µs
Notes: 1. In ATmega64A, this parameter is characterized and not 100% tested.
331
8160C–AVR–07/09
ATMEL [ ATMEL ]
