ATmega64A
Figure 23-5. ADC Timing Diagram, Single Conversion
One Conversion
Next Conversion
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
MSB of Result
LSB of Result
ADCL
Sample & Hold
Conversion
Complete
MUX and REFS
Update
MUX and REFS
Update
Figure 23-6. ADC Timing Diagram, Auto Triggered Conversion
One Conversion
Next Conversion
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
MSB of Result
LSB of Result
Sample &
Hold
Prescaler
Reset
Conversion
Complete
Prescaler
Reset
MUX and REFS
Update
Figure 23-7. ADC Timing Diagram, Free Running Conversion
One Conversion
Next Conversion
11
12
13
1
2
3
4
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
MSB of Result
LSB of Result
Sample & Hold
MUX and REFS
Update
Conversion
Complete
238
8160C–AVR–07/09
ATMEL [ ATMEL ]
