ATmega64A
Figure 7-2. Data Memory Map
Memory Configuration A
Memory Configuration B
Data Memory
Data Memory
$0000 - $001F
$0020 - $005F
160 Ext I/O Reg. $0060 - $00FF
32 Registers
64 I/O Registers $0020 - $005F
$0060
$0000 - $001F
32 Registers
64 I/O Registers
Internal SRAM
(4000 x 8)
$0100
Internal SRAM
$0FFF
$1000
(4096 x 8)
$10FF
$1100
External SRAM
(0 - 64K x 8)
External SRAM
(0 - 64K x 8)
$FFFF
$FFFF
7.2.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clkCPU cycles as described in Figure 7-3.
20
8160C–AVR–07/09