ATmega64A
20. USART
20.1 Features
• Full Duplex Operation (Independent Serial Receive and Transmit Registers)
• Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation
• High Resolution Baud Rate Generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data OverRun Detection
• Framing Error Detection
• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
• Multi-processor Communication Mode
• Double Speed Asynchronous Communication Mode
20.1.1
Dual USART
The ATmega64A has two USART’s, USART0 and USART1. The functionality for both USART’s
is described below. USART0 and USART1 have different I/O Registers as shown in “Register
Summary” on page 373. Note that in ATmega103 compatibility mode, USART1 is not available,
neither is the UBRR0H or UCRS0C registers. This means that in ATmega103 compatibility
mode, the ATmega64A supports asynchronous operation of USART0 only.
20.2 Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device.
A simplified block diagram of the USART Transmitter is shown in Figure 20-1. CPU accessible
I/O Registers and I/O pins are shown in bold.
174
8160C–AVR–07/09
ATMEL [ ATMEL ]
