ATmega64A
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have
no effect on the slave. The relationship between SCK and the Oscillator Clock frequency fosc is
shown in Table 19-5.
Table 19-5. Relationship Between SCK and the Oscillator Frequency
SPI2X
SPR1
SPR0
SCK Frequency
fosc/4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fosc/16
fosc/64
fosc/128
fosc/2
fosc/8
fosc/32
fosc/64
19.5.2
SPSR – SPI Status Register
Bit
7
SPIF
R
6
5
–
4
–
3
–
2
–
1
–
0
SPI2X
R/W
0
0x0E (0x2E)
Read/Write
Initial Value
WCOL
SPSR
R
0
R
0
R
0
R
0
R
0
R
0
0
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
• Bit 5:1 – Res: Reserved Bits
These bits are reserved bits in the ATmega64A and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see Table 19-5). This means that the minimum SCK period will be two CPU
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fosc/4
or lower.
The SPI interface on the ATmega64A is also used for program memory and EEPROM down-
loading or uploading. See page 309 for SPI Serial Programming and verification.
172
8160C–AVR–07/09
ATMEL [ ATMEL ]
