ATmega64A
A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2 as TOP.
The FOC2 bit is always read as zero.
• Bit 6, 3 – WGM21:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See Table 17-2 and “Modes of Operation”
on page 151.
Table 17-2. Waveform Generation Mode Bit Description(1)
WGM21
(CTC2)
WGM20
(PWM2)
Timer/Counter Mode of
Operation
Update of
OCR2
TOV2 Flag
Set on
Mode
TOP
0
1
2
3
0
0
1
1
0
1
0
1
Normal
0xFF
0xFF
OCR2
0xFF
Immediate
TOP
MAX
PWM, Phase Correct
CTC
BOTTOM
MAX
Immediate
BOTTOM
Fast PWM
MAX
Note:
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
However, the functionality and location of these bits are compatible with previous versions of
the timer.
• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits
are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to the OC2 pin must be
set in order to enable the output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0
bit setting. Table 17-3 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a
Normal or CTC mode (non-PWM).
Table 17-3. Compare Output Mode, non-PWM Mode
COM21
COM20
Description
0
0
1
1
0
1
0
1
Normal port operation, OC2 disconnected.
Toggle OC2 on Compare Match.
Clear OC2 on Compare Match.
Set OC2 on Compare Match.
158
8160C–AVR–07/09
ATMEL [ ATMEL ]
