ATmega64A
14.7.4
Phase Correct PWM Mode
The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM
waveform generation option. The phase correct PWM mode is based on a dual-slope operation.
The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-
inverting Compare Output mode, the Output Compare (OC0) is cleared on the Compare Match
between TCNT0 and OCR0 while upcounting, and set on the Compare Match while downcount-
ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has
lower maximum operation frequency than single slope operation. However, due to the symmet-
ric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct
PWM mode the counter is incremented until the counter value matches MAX. When the counter
reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one
timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 14-7.
The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal
line marks on the TCNT0 slopes represent Compare Matches between OCR0 and TCNT0.
Figure 14-7. Phase Correct PWM Mode, Timing Diagram
OCn Interrupt
Flag Set
OCRn Update
TOVn Interrupt
Flag Set
TCNTn
(COMn1:0 = 2)
OCn
(COMn1:0 = 3)
OCn
1
2
3
Period
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The
interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0 pin. Setting the COM01:0 bits to two will produce a non-inverted PWM. An inverted PWM
output can be generated by setting the COM01:0 to three (See Table 14-5 on page 107). The
actual OC0 value will only be visible on the port pin if the data direction for the port pin is set as
output. The PWM waveform is generated by clearing (or setting) the OC0 Register at the Com-
100
8160C–AVR–07/09
ATMEL [ ATMEL ]
