ATmega48PA/88PA/168PA/328P
Figure 21-12. Formats and States in the Master Transmitter Mode
MT
Successfull
transmission
to a slave
receiver
S
SLA
W
A
DATA
A
P
$08
$18
$28
Next transfer
started with a
repeated start
condition
RS
SLA
W
R
$10
Not acknowledge
received after the
slave address
A
P
$20
MR
Not acknowledge
received after a data
byte
A
P
$30
Arbitration lost in slave
address or data byte
Other master
continues
Other master
continues
A or A
A or A
$38
A
$38
Arbitration lost and
addressed as slave
Other master
continues
To corresponding
states in slave mode
$68 $78 $B0
Any number of data bytes
and their associated acknowledge bits
From master to slave
From slave to master
DATA
A
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
n
21.7.2
Master Receiver Mode
In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter
(Slave see Figure 21-13). In order to enter a Master mode, a START condition must be transmit-
ted. The format of the following address packet determines whether Master Transmitter or
Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R
is transmitted, MR mode is entered. All the status codes mentioned in this section assume that
the prescaler bits are zero or are masked to zero.
230
8161D–AVR–10/09
ATMEL [ ATMEL ]
