欢迎访问ic37.com |
会员登录 免费注册
发布采购

ATMEGA48PA-AU 参数 Datasheet PDF下载

ATMEGA48PA-AU图片预览
型号: ATMEGA48PA-AU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器与4/8/ 16 / 32K字节的系统内可编程闪存 [8-bit Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 448 页 / 12817 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA48PA-AU的Datasheet PDF文件第225页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第226页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第227页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第228页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第230页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第231页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第232页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第233页  
ATmega48PA/88PA/168PA/328P  
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same  
Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables  
the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode with-  
out losing control of the bus.  
Table 21-2. Status codes for Master Transmitter Mode  
Status Code  
(TWSR)  
Prescaler Bits  
are 0  
Application Software Response  
To/from TWDR To TWCR  
STO TWIN  
Status of the 2-wire Serial Bus  
and 2-wire Serial Interface  
Hardware  
STA  
0
TWE  
A
Next Action Taken by TWI Hardware  
T
0x08  
0x10  
A START condition has been  
transmitted  
Load SLA+W  
0
1
X
SLA+W will be transmitted;  
ACK or NOT ACK will be received  
A repeated START condition  
has been transmitted  
Load SLA+W or  
Load SLA+R  
0
0
0
0
1
1
X
X
SLA+W will be transmitted;  
ACK or NOT ACK will be received  
SLA+R will be transmitted;  
Logic will switch to Master Receiver mode  
0x18  
0x20  
0x28  
0x30  
0x38  
SLA+W has been transmitted;  
ACK has been received  
Load data byte or  
0
0
1
X
Data byte will be transmitted and ACK or NOT ACK will  
be received  
Repeated START will be transmitted  
STOP condition will be transmitted and  
TWSTO Flag will be reset  
No TWDR action or  
No TWDR action or  
1
0
0
1
1
1
X
X
No TWDR action  
Load data byte or  
1
0
1
0
1
1
X
X
STOP condition followed by a START condition will be  
transmitted and TWSTO Flag will be reset  
SLA+W has been transmitted;  
NOT ACK has been received  
Data byte will be transmitted and ACK or NOT ACK will  
be received  
Repeated START will be transmitted  
STOP condition will be transmitted and  
TWSTO Flag will be reset  
No TWDR action or  
No TWDR action or  
1
0
0
1
1
1
X
X
No TWDR action  
Load data byte or  
1
0
1
0
1
1
X
X
STOP condition followed by a START condition will be  
transmitted and TWSTO Flag will be reset  
Data byte has been transmit-  
ted;  
ACK has been received  
Data byte will be transmitted and ACK or NOT ACK will  
be received  
Repeated START will be transmitted  
STOP condition will be transmitted and  
TWSTO Flag will be reset  
No TWDR action or  
No TWDR action or  
1
0
0
1
1
1
X
X
No TWDR action  
Load data byte or  
1
0
1
0
1
1
X
X
STOP condition followed by a START condition will be  
transmitted and TWSTO Flag will be reset  
Data byte has been transmit-  
ted;  
NOT ACK has been received  
Data byte will be transmitted and ACK or NOT ACK will  
be received  
Repeated START will be transmitted  
STOP condition will be transmitted and  
TWSTO Flag will be reset  
No TWDR action or  
No TWDR action or  
1
0
0
1
1
1
X
X
No TWDR action  
1
1
1
X
STOP condition followed by a START condition will be  
transmitted and TWSTO Flag will be reset  
Arbitration lost in SLA+W or  
data bytes  
No TWDR action or  
No TWDR action  
0
1
0
0
1
1
X
X
2-wire Serial Bus will be released and not addressed  
Slave mode entered  
A START condition will be transmitted when the bus  
becomes free  
229  
8161D–AVR–10/09  
 复制成功!