ATmega48PA/88PA/168PA/328P
The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different.
When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A
and TCCR2B the value in the temporary storage register is read.
17.11.9 GTCCR – General Timer/Counter Control Register
Bit
0x23 (0x43)
7
6
5
4
–
3
–
2
–
1
0
TSM
–
–
PSRASY PSRSYNC
GTCCR
Read/Write
Initial Value
R/W
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared
immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous
mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by
hardware if the TSM bit is set. Refer to the description of the ”Bit 7 – TSM: Timer/Counter Syn-
chronization Mode” on page 143 for a description of the Timer/Counter Synchronization mode.
165
8161D–AVR–10/09
ATMEL [ ATMEL ]
