ATmega16/32/64/M1/C1
10.2.4
Pin Change Interrupt Flag Register - PCIFR
Bit
7
–
6
–
5
–
4
–
3
PCIF3
R
2
PCIF2
R/W
0
1
PCIF1
R/W
0
0
PCIF0
R/W
0
PCIFR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
0
• Bit 7..4 - Res: Reserved Bits
These bits are unused bits in the ATmega16/32/64/M1/C1, and will always read as zero.
• Bit 3 - PCIF3: Pin Change Interrupt Flag 3
When a logic change on any PCINT26..24 pin triggers an interrupt request, PCIF3 becomes set
(one). If the I-bit in SREG and the PCIE3 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 2 - PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set
(one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 1 - PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 0 - PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
10.2.5
Pin Change Mask Register 3 – PCMSK3
Bit
7
6
5
-
4
-
3
-
2
PCINT26
R/W
0
1
PCINT25
R/W
0
0
PCINT24
R/W
0
-
-
PCMSK3
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bit 7..3 – Res: Reserved Bit
These bits are unused bits in the ATmega16/32/64/M1/C1, and will always read as zero.
• Bit 2..0 – PCINT26..24: Pin Change Enable Mask 26..24
Each PCINT26..24-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT26..24 is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT23..24 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
85
7647F–AVR–04/09
ATMEL [ ATMEL ]
