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ATMEGA16M1_1 参数 Datasheet PDF下载

ATMEGA16M1_1图片预览
型号: ATMEGA16M1_1
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,带有16K / 32K / 64K字节的系统内可编程闪存 [8-bit Microcontroller with 16K/32K/64K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 365 页 / 6381 K
品牌: ATMEL [ ATMEL ]
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5.5.1  
Oscillator Calibration Register – OSCCAL  
Bit  
7
6
5
4
3
2
1
0
CAL7  
R/W  
CAL6  
R/W  
CAL5  
R/W  
CAL4  
R/W  
CAL3  
R/W  
CAL2  
R/W  
CAL1  
R/W  
CAL0  
R/W  
OSCCAL  
Read/Write  
Initial Value  
Device Specific Calibration Value  
• Bits 7..0 – CAL7..0: Oscillator Calibration Value  
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to  
remove process variations from the oscillator frequency. The factory-calibrated value is automat-  
ically written to this register during chip reset, giving an oscillator frequency of 8.0 MHz at 25°C.  
The application software can write this register to change the oscillator frequency. The oscillator  
can be calibrated to any frequency in the range 7.3 - 8.1 MHz within ±1% accuracy. Calibration  
outside that range is not guaranteed.  
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write  
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more  
than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.  
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the  
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-  
quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher  
frequency than OSCCAL = 0x80.  
The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00  
gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the  
range. Incrementing CAL6..0 by 1 will give a frequency increment of less than 2% in the fre-  
quency range 7.3 - 8.1 MHz.  
5.6  
PLL  
5.6.1  
Internal PLL  
The internal PLL in ATmega16/32/64/M1/C1 generates a clock frequency that is 64x multiplied  
from its nominal 1 MHz input. The source of the 1 MHz PLL input clock can be:  
• the output of the internal RC Oscillator divided by 8  
• the output of the Crystal Oscillator divided by 8  
• the external clock divided by 8  
See the Figure 5-3 on page 35.  
When the PLL is locked on the RC Oscillator, adjusting the RC Oscillator via OSCCAL Register,  
will also modify the PLL clock output. However, even if the possibly divided RC Oscillator is  
taken to a higher frequency than 8 MHz, the PLL output clock frequency saturates at 70 MHz  
(worst case) and remains oscillating at the maximum frequency. It should be noted that the PLL  
in this case is not locked any more with its 1MHz source clock.  
Therefore it is recommended not to take the OSCCAL adjustments to a higher frequency than 8  
MHz in order to keep the PLL in the correct operating range.  
The internal PLL is enabled only when the PLLE bit in the register PLLCSR is set. The bit  
PLOCK from the register PLLCSR is set when PLL is locked.  
Both internal 8 MHz RC Oscillator, Crystal Oscillator and PLL are switched off in Power-down  
and Standby sleep modes.04/09  
34  
ATmega16/32/64/M1/C1  
7647F–AVR–04/09  
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