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ATMEGA48V-10AUR 参数 Datasheet PDF下载

ATMEGA48V-10AUR图片预览
型号: ATMEGA48V-10AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 10MHz, CMOS, PQFP32, 7 X 7 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ABA, TQFP-32]
分类和应用: 闪存微控制器
文件页数/大小: 376 页 / 4764 K
品牌: ATMEL [ ATMEL ]
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Figure 21-16. Formats and States in the Slave Receiver Mode  
Reception of the own  
S
SLA  
W
A
DATA  
A
DATA  
A
P or S  
slave address and one or  
more data bytes. All are  
acknowledged  
$60  
$80  
$80  
A
$A0  
Last data byte received  
is not acknowledged  
P or S  
$88  
Arbitration lost as master  
and addressed as slave  
A
$68  
A
Reception of the general call  
address and one or more data  
bytes  
General Call  
DATA  
A
DATA  
A
P or S  
$70  
$90  
$90  
A
$A0  
Last data byte received is  
not acknowledged  
P or S  
$98  
Arbitration lost as master and  
addressed as slave by general call  
A
$78  
Any number of data bytes  
and their associated acknowledge bits  
From master to slave  
From slave to master  
DATA  
A
This number (contained in TWSR) corresponds  
to a defined state of the 2-Wire Serial Bus. The  
prescaler bits are zero or masked to zero  
n
21.7.4  
Slave Transmitter Mode  
In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver  
(see Figure 21-17). All the status codes mentioned in this section assume that the prescaler bits  
are zero or are masked to zero.  
Figure 21-17. Data Transfer in Slave Transmitter Mode  
VCC  
Device 1  
SLAVE  
TRANSMITTER  
Device 2  
MASTER  
RECEIVER  
Device 3  
Device n  
R1  
R2  
........  
SDA  
SCL  
232  
ATmega48/88/168  
2545M–AVR–09/07  
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