Input Capture Register
1 – ICR1H and ICR1L
Bit
7
6
5
4
3
2
1
0
ICR1[15:8]
ICR1[7:0]
ICR1H
ICR1L
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
0
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator Output for Timer/Counter1). The Input Cap-
ture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 79.
Timer/Counter
Bit
7
OCIE2
R/W
0
6
TOIE2
R/W
0
5
TICIE1
R/W
0
4
OCIE1A
R/W
0
3
OCIE1B
R/W
0
2
TOIE1
R/W
0
1
–
0
TOIE0
R/W
0
Interrupt Mask
Register – TIMSK(1)
TIMSK
Read/Write
Initial Value
R
0
Note:
1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are
described in this section. The remaining bits are described in their respective timer sections.
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture Interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 46) is executed when the ICF1 Flag, located in TIFR, is set.
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 46) is executed when the OCF1A Flag, located in
TIFR, is set.
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 46) is executed when the OCF1B Flag, located in
TIFR, is set.
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector
(see “Interrupts” on page 46) is executed when the TOV1 Flag, located in TIFR, is set.
Timer/Counter
Interrupt Flag Register
– TIFR(1)
Bit
7
OCF2
R/W
0
6
TOV2
R/W
0
5
4
OCF1A
R/W
0
3
OCF1B
R/W
0
2
TOV1
R/W
0
1
–
0
TOV0
R/W
0
ICF1
R/W
0
TIFR
Read/Write
Initial Value
R
0
Note:
1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described
in this section. The remaining bits are described in their respective timer sections.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
102
ATmega8(L)
2486T–AVR–05/08
ATMEL [ ATMEL ]
