ATmega48/88/168
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in
the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE
and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use-
ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and
System Reset Mode, WDIE must be set after each interrupt. This should however not be done
within the interrupt service routine itself, as this might compromise the safety-function of the
Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a Sys-
tem Reset will be applied.
Table 10-1. Watchdog Timer Configuration
WDTON(1)
WDE
WDIE
Mode
Action on Time-out
None
1
1
1
0
0
1
0
1
0
Stopped
Interrupt Mode
System Reset Mode
Interrupt
Reset
Interrupt and System Reset
Mode
Interrupt, then go to System
Reset Mode
1
0
1
x
1
x
System Reset Mode
Reset
Note:
1. WDTON Fuse set to “0“ means programmed and “1“ means unprogrammed.
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-
ditions causing failure, and a safe start-up after the failure.
55
2545M–AVR–09/07
ATMEL [ ATMEL ]
