Table 11-1. Reset and Interrupt Vectors in ATmega48 (Continued)
Vector No. Program Address Source Interrupt Definition
22
23
24
25
26
0x015
0x016
0x017
0x018
0x019
ADC
ADC Conversion Complete
EEPROM Ready
EE READY
ANALOG COMP
TWI
Analog Comparator
2-wire Serial Interface
Store Program Memory Ready
SPM READY
The most typical and general program setup for the Reset and Interrupt Vector Addresses in
ATmega48 is:
Address Labels Code
Comments
0x000
0x001
0x002
0x003
0x004
0x005
0x006
0x007
0x008
0x009
0x00A
0x00B
0x00C
0x00D
0x00E
0x00F
0x010
0x011
0x012
0x013
0x014
0x015
0x016
0x017
0x018
0x019
;
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
RESET
; Reset Handler
EXT_INT0
EXT_INT1
PCINT0
; IRQ0 Handler
; IRQ1 Handler
; PCINT0 Handler
PCINT1
; PCINT1 Handler
PCINT2
; PCINT2 Handler
WDT
; Watchdog Timer Handler
; Timer2 Compare A Handler
; Timer2 Compare B Handler
; Timer2 Overflow Handler
; Timer1 Capture Handler
; Timer1 Compare A Handler
; Timer1 Compare B Handler
; Timer1 Overflow Handler
; Timer0 Compare A Handler
; Timer0 Compare B Handler
; Timer0 Overflow Handler
; SPI Transfer Complete Handler
; USART, RX Complete Handler
; USART, UDR Empty Handler
; USART, TX Complete Handler
; ADC Conversion Complete Handler
; EEPROM Ready Handler
; Analog Comparator Handler
; 2-wire Serial Interface Handler
; Store Program Memory Ready Handler
TIM2_COMPA
TIM2_COMPB
TIM2_OVF
TIM1_CAPT
TIM1_COMPA
TIM1_COMPB
TIM1_OVF
TIM0_COMPA
TIM0_COMPB
TIM0_OVF
SPI_STC
USART_RXC
USART_UDRE
USART_TXC
ADC
EE_RDY
ANA_COMP
TWI
SPM_RDY
0x01ARESET:
0x01B
0x01C
0x01D
0x01E
0x01F
ldi
out
ldi
out
sei
r16, high(RAMEND); Main program start
SPH,r16
; Set Stack Pointer to top of RAM
r16, low(RAMEND)
SPL,r16
; Enable interrupts
<instr> xxx
... ...
...
...
58
ATmega48/88/168
2545M–AVR–09/07
ATMEL [ ATMEL ]
